Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29005
Change subject: soc/intel/cannonlake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled ......................................................................
soc/intel/cannonlake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. Function to set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as well as S3 resume path (BS_OS_RESUME).
Change-Id: I4ab3bbba1da79dbf1790c99c611195cffbda1511 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/pmc.c 1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29005/1
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index ecd47e0..02b91cd 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -160,3 +160,28 @@ * allocate resources. */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); + +/* + * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in + * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable + * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE# + * pin. + */ +static void pm1_handle_wake_pin(void *unused) +{ + struct device *dev = SA_DEV_ROOT; + + if (!dev || !dev->chip_info) + return; + + const config_t *conf = dev->chip_info; + + /* If WAKE# pin is enabled, bail out early. */ + if (conf->deep_sx_config & DSX_EN_WAKE_PIN) + return; + + pmc_update_pm1_enable(PCIEXPWAK_DIS); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_handle_wake_pin, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_EXIT, pm1_handle_wake_pin, NULL);