New patch to review for coreboot: ca986c8 mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5401

-gerrit

commit ca986c8c0d9b0e8cfbb54cc615bc83de5628ca58
Author: Edward O'Callaghan 
Date:   Sun Mar 23 20:42:02 2014 +1100

mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb

Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
    Signed-off-by: Edward O'Callaghan 
---
 src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 7160f33..433336e 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -96,7 +96,7 @@ chip northbridge/amd/agesa/family14/root_complex
 # $ sudo isadump 0x4e 0x4f 0x7
 # which select logical device (LDN) 7. Then read that we have in 0x27, bit1
    					device pnp 2e.07 off end	# BSEL
-						device pnp 2e.0a off end	# PME
+						device pnp 2e.0a on end	# PME
    				end # f71869ad
    			end #LPC
    			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}