[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Angel Pons, Ronak Kanabar.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 )
Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74158/comment/3b085fae_61aa0d68 PS3, Line 8:
Please describe the problem, including what CAT means, and maybe a reference to the documentation […]
I would directly write the whole thing (makes it easier to understand for me personally): "Detectable but Uncorrected Errors (DUE) can manifest themselves via blue screens or other system hangs/crashes. In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a three-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. Identifying the root cause of such events is notoriously difficult, as the system is effectively wedged and cannot be put into probe mode by JTAG-assisted hardware debuggers. In such extreme cases the machine check error handler at vector 0x18h does not execute correctly and no register information is captured." source: https://www.asset-intertech.com/resources/blog/2015/12/catastrophic-errors-i...
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Maximilian Brune (Code Review)