Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This changes uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4b5a39..9506738 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -121,7 +121,11 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 14.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on end # I2C0 0xA0E8 device pci 15.1 on end # I2C1 0xA0E9 device pci 15.2 on end # I2C2 0xA0EA
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39315/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39315/1//COMMIT_MSG@9 PS1, Line 9: changes change (no "s" on the end)
https://review.coreboot.org/c/coreboot/+/39315/1//COMMIT_MSG@9 PS1, Line 9: for CNVi device and Would be good to include fact this CL exports a wake gpio, perhaps something like "for CNVi device, exports a wake gpio, and"
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, caveh jalali, Nick Vaccaro, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39315
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39315/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39315/1//COMMIT_MSG@9 PS1, Line 9: changes
change (no "s" on the end)
Done
https://review.coreboot.org/c/coreboot/+/39315/1//COMMIT_MSG@9 PS1, Line 9: for CNVi device and
Would be good to include fact this CL exports a wake gpio, perhaps something like "for CNVi device, […]
Done
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 2: Code-Review+2
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 2: Code-Review+1
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, caveh jalali, Nick Vaccaro, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39315
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 3: Code-Review+2
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, caveh jalali, Nick Vaccaro, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39315
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/4
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 4: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39315/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
PS4: you may want to rebase this again to get rid of the audio changes.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39315/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
PS4:
you may want to rebase this again to get rid of the audio changes.
I did rebase for removing the conflict with audio changes. Currently there are no merge conflicts with this CL. Let me know if you still see conflicts.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 4:
Can you also add change for UP4?
Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Nick Vaccaro, Raj Astekar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39315
to look at the new patch set (#5).
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 10 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/5
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 5: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 5: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 5: Code-Review+1
ke
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 10 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5888db0..e60e648 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -136,7 +136,11 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index a937ab3..a3539aa 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -131,7 +131,11 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4"
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 6: Code-Review+2