Change in coreboot[master]: i82371eb: Roll 82093aa init into isa_init()

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38599 )

Change subject: i82371eb: Roll 82093aa init into isa_init()
......................................................................

i82371eb: Roll 82093aa init into isa_init()

This allows reuse of dev and reg32 already available,
and converting the block from #if to simple if.

Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659
Signed-off-by: Keith Hui 
---
M src/southbridge/intel/i82371eb/isa.c
1 file changed, 22 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38599/1

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 1442470..310a9fe 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -30,37 +30,6 @@
 #include "i82371eb.h"
 #include "chip.h"

-#if CONFIG(IOAPIC)
-static void enable_intel_82093aa_ioapic(void)
-{
-	u16 reg16;
-	u32 reg32;
-	u8 ioapic_id = 2;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-	struct device *dev;
-
-	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
-			      PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
-
-	/* Enable IOAPIC. */
-	reg16 = pci_read_config16(dev, XBCS);
-	reg16 |= (1 << 8); /* APIC Chip Select */
-	pci_write_config16(dev, XBCS, reg16);
-
-	/* Set the IOAPIC ID. */
-	*ioapic_index = 0;
-	*ioapic_data = ioapic_id << 24;
-
-	/* Read back and verify the IOAPIC ID. */
-	*ioapic_index = 0;
-	reg32 = (*ioapic_data >> 24) & 0x0f;
-	printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
-	if (reg32 != ioapic_id)
-		die("IOAPIC error!\n");
-}
-#endif
-
 static void isa_init(struct device *dev)
 {
    u32 reg32;
@@ -91,7 +60,6 @@
    /* Initialize ISA DMA. */
    isa_dma_init();

-#if CONFIG(IOAPIC)
    /*
     * Unlike most other southbridges the 82371EB doesn't have a built-in
     * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@@ -100,8 +68,28 @@
     * Thus, we can/must only enable the IOAPIC if it actually exists,
     * i.e. the respective mainboard does "select IOAPIC".
     */
-	enable_intel_82093aa_ioapic();
-#endif
+	if (CONFIG(IOAPIC)) {
+		u16 reg16;
+		u8 ioapic_id = 2;
+		volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+		volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+		/* Enable IOAPIC. */
+		reg16 = pci_read_config16(dev, XBCS);
+		reg16 |= (1 << 8); /* APIC Chip Select */
+		pci_write_config16(dev, XBCS, reg16);
+
+		/* Set the IOAPIC ID. */
+		*ioapic_index = 0;
+		*ioapic_data = ioapic_id << 24;
+
+		/* Read back and verify the IOAPIC ID. */
+		*ioapic_index = 0;
+		reg32 = (*ioapic_data >> 24) & 0x0f;
+		printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+		if (reg32 != ioapic_id)
+			die("IOAPIC error!\n");
+	}
 }

static void sb_read_resources(struct device *dev)

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38599 )

Change subject: i82371eb: Roll 82093aa init into isa_init()
......................................................................

Patch Set 2: Code-Review+1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38599 )

Change subject: i82371eb: Roll 82093aa init into isa_init()
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38599 )

Change subject: i82371eb: Roll 82093aa init into isa_init()
......................................................................

i82371eb: Roll 82093aa init into isa_init()

This allows reuse of dev and reg32 already available,
and converting the block from #if to simple if.

Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38599
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Angel Pons 
---
M src/southbridge/intel/i82371eb/isa.c
1 file changed, 22 insertions(+), 34 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index fefead0..bdad959 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -30,37 +30,6 @@
 #include "i82371eb.h"
 #include "chip.h"

-#if CONFIG(IOAPIC)
-static void enable_intel_82093aa_ioapic(void)
-{
-	u16 reg16;
-	u32 reg32;
-	u8 ioapic_id = 2;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-	struct device *dev;
-
-	dev = dev_find_device(PCI_VENDOR_ID_INTEL,
-			      PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
-
-	/* Enable IOAPIC. */
-	reg16 = pci_read_config16(dev, XBCS);
-	reg16 |= (1 << 8); /* APIC Chip Select */
-	pci_write_config16(dev, XBCS, reg16);
-
-	/* Set the IOAPIC ID. */
-	*ioapic_index = 0;
-	*ioapic_data = ioapic_id << 24;
-
-	/* Read back and verify the IOAPIC ID. */
-	*ioapic_index = 0;
-	reg32 = (*ioapic_data >> 24) & 0x0f;
-	printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
-	if (reg32 != ioapic_id)
-		die("IOAPIC error!\n");
-}
-#endif
-
 static void isa_init(struct device *dev)
 {
    u32 reg32;
@@ -90,7 +59,6 @@
    /* Initialize ISA DMA. */
    isa_dma_init();

-#if CONFIG(IOAPIC)
    /*
     * Unlike most other southbridges the 82371EB doesn't have a built-in
     * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@@ -99,8 +67,28 @@
     * Thus, we can/must only enable the IOAPIC if it actually exists,
     * i.e. the respective mainboard does "select IOAPIC".
     */
-	enable_intel_82093aa_ioapic();
-#endif
+	if (CONFIG(IOAPIC)) {
+		u16 reg16;
+		u8 ioapic_id = 2;
+		volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+		volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+		/* Enable IOAPIC. */
+		reg16 = pci_read_config16(dev, XBCS);
+		reg16 |= (1 << 8); /* APIC Chip Select */
+		pci_write_config16(dev, XBCS, reg16);
+
+		/* Set the IOAPIC ID. */
+		*ioapic_index = 0;
+		*ioapic_data = ioapic_id << 24;
+
+		/* Read back and verify the IOAPIC ID. */
+		*ioapic_index = 0;
+		reg32 = (*ioapic_data >> 24) & 0x0f;
+		printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
+		if (reg32 != ioapic_id)
+			die("IOAPIC error!\n");
+	}
 }

static void sb_read_resources(struct device *dev)

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38599 )

Change subject: i82371eb: Roll 82093aa init into isa_init()
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1053
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1052
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1051

Please note: This test is under development and might not be accurate at all!