[S] Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common power limit code

[Angel Pons (Code Review)]

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Kyösti Mälkki, Patrick Rudolph.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61017 )

Change subject: soc/intel/denverton_ns: enable Denverton to use common power limit code
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Patch Set 13: Code-Review+1

(1 comment)

File src/soc/intel/denverton_ns/systemagent.c:

https://review.coreboot.org/c/coreboot/+/61017/comment/a8b1d487_888d64e3 
PS13, Line 80: 	pci_write_config32(dev, BGSM, sareg);
> Huh.. memory layout must happen late romstage, not late ramstage. Not related to this patch, though.

Marking as resolved then