New patch to review for coreboot: ddr3: Fix SPD CRC calculation

[Patrick Rudolph]

Patrick Rudolph ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10629

-gerrit

commit 7400cd88379a158ede0581c181290dcdd5548a7e
Author: Patrick Rudolph 
Date:   Mon Jun 22 19:32:53 2015 +0200

ddr3: Fix SPD CRC calculation

Use the correct SPD size for crc calculation. sizeof(*spd) returns 4
    while sizeof(spd_raw_data) returns the expected value of 256.

Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f
    Signed-off-by: Patrick Rudolph 
---
 src/device/dram/ddr3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index 8170ae1..c10741b 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -128,7 +128,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
    dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3;
    dimm->dimm_type = spd[3] & 0xf;

-	crc = spd_ddr3_calc_crc(spd, sizeof(*spd));
+	crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data));
    /* Compare with the CRC in the SPD */
    spd_crc = (spd[127] << 8) + spd[126];
    /* Verify the CRC is correct */