Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50491 )
Change subject: sb/intel/x/lpc.c: Drop commented-out `gpio_init` call ......................................................................
sb/intel/x/lpc.c: Drop commented-out `gpio_init` call
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 3 files changed, 0 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/50491/1
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8bdaa5a..7f648a9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -529,9 +529,6 @@ printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); }
- /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ sb_rtc_init();
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a8bc7e3..a44bbf9 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -335,9 +335,6 @@ /* Configure Cx state registers */ i82801gx_configure_cstates(dev);
- /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ i82801gx_rtc_init(dev);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0a96473..3309283 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -431,9 +431,6 @@ /* Initialize power management */ mobile5_pm_init(dev);
- /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ pch_rtc_init(dev);