New patch to review for coreboot: northbridge/amd/amdfam10: transition away from device_t
Antonello Dettori (dev@dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16466
-gerrit
commit ec7942b5696ce006cd29a36b7736674cc93715f3 Author: Antonello Dettori dev@dettori.io Date: Sat Sep 3 10:45:33 2016 +0200
northbridge/amd/amdfam10: transition away from device_t
Replace the use of the old device_t definition inside northbridge/amd/amdfam10.
Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949 Signed-off-by: Antonello Dettori dev@dettori.io --- src/northbridge/amd/amdfam10/amdfam10.h | 8 +++++--- src/northbridge/amd/amdfam10/debug.c | 8 ++++---- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdfam10/pci.c | 11 +++++++---- src/northbridge/amd/amdfam10/raminit.h | 4 ++-- src/northbridge/amd/amdfam10/setup_resource_map.c | 8 ++++---- 6 files changed, 23 insertions(+), 18 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index c0bfc5a..4c3aec6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -984,10 +984,10 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #endif
struct link_pair_t { - device_t udev; + pci_devfn_t udev; u32 upos; u32 uoffs; - device_t dev; + pci_devfn_t dev; u32 pos; u32 offs; u8 host; @@ -1048,7 +1048,7 @@ device_t get_node_pci(u32 nodeid, u32 fn); #endif
#ifdef __PRE_RAM__ -void showallroutes(int level, device_t dev); +void showallroutes(int level, pci_devfn_t dev);
void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base); @@ -1072,9 +1072,11 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
struct acpi_rsdp;
+#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(device_t device); +#endif
#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index f8e5358..e01c44d 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -34,7 +34,7 @@ static void print_debug_pci_dev(u32 dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -59,7 +59,7 @@ static inline void print_pci_devices(void)
static inline void print_pci_devices_on_bus(u32 busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -160,7 +160,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -185,7 +185,7 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(u32 busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 57c992c..a1b411f 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -93,7 +93,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (next_unitid>=0x18) { diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 5892540..03b63b5 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -19,7 +19,7 @@ /* bit [10,8] are dev func, bit[1,0] are dev index */
-static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) +static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) { u32 dword;
@@ -29,7 +29,8 @@ static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) }
#ifdef UNUSED_CODE -static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, + u32 data) {
pci_write_config32(dev, index_reg, index); @@ -39,7 +40,8 @@ static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 } #endif
-static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) +static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, + u32 index) {
u32 dword; @@ -54,7 +56,8 @@ static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) }
#ifdef UNUSED_CODE -static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data) +static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, + u32 index, u32 data) {
u32 dword; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 622a98a..7c7065df 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -23,7 +23,7 @@ #define DIMM_SOCKETS 8 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3, f4, f5; + pci_devfn_t f0, f1, f2, f3, f4, f5; /* channelA, channelB belong to DCT0, * channelC, channelD belong to DCT1 * Each DCT may support one ganged logical FBDIMM ---> 128 bit @@ -47,7 +47,7 @@ struct mem_controller { #define DIMM_SOCKETS 4 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3, f4, f5; + pci_devfn_t f0, f1, f2, f3, f4, f5; /* channel0 is DCT0 --- channelA * channel1 is DCT1 --- channelB * can be ganged, a single dual-channel DCT ---> 128 bit diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index a14fc3c..6de7a8c 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -23,7 +23,7 @@ static void setup_resource_map(const u32 *register_values, u32 max) // printk(BIOS_DEBUG, "setting up resource map....");
for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg;
@@ -43,7 +43,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p u32 i; // printk(BIOS_DEBUG, "setting up resource map offset...."); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; unsigned long reg; dev = (register_values[i] & ~0xfff) + offset_pci_dev; @@ -79,7 +79,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; @@ -147,7 +147,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max) switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = register_values[i+1] & ~0xff;
-
Antonello Dettori