Change in coreboot[master]: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43397 )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
soc/intel/skylake: Add necessary FSPT params when FSP CAR is used
Without these parameters the build with FSP CAR enabled will fail, unless a board implement the parameters.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I7b3f770bd56ca072bebb485c02e1022ba95c6e4c --- M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/bootblock/fspcar.c 2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/43397/1
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 75121ab..842f582 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc
+bootblock-$(CONFIG_FSP_CAR) += bootblock/fspcar.c bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c diff --git a/src/soc/intel/skylake/bootblock/fspcar.c b/src/soc/intel/skylake/bootblock/fspcar.c new file mode 100644 index 0000000..b2580c4 --- /dev/null +++ b/src/soc/intel/skylake/bootblock/fspcar.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <FsptUpd.h> + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = 0x545F4450554C424BULL, /* 'KBLUPD_T' */ + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionSize = 0, + .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, + }, +};
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43397 )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/fspcar.c:
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... PS1, Line 26: CONFIG_ROM_SIZE that explodes if CONFIG_ROM_SIZE > 16MiB
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43397 )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/fspcar.c:
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... PS1, Line 26: CONFIG_ROM_SIZE
that explodes if CONFIG_ROM_SIZE > 16MiB
True. Any suggestions to resolve it?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43397 )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/fspcar.c:
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... PS1, Line 26: CONFIG_ROM_SIZE
True. […]
I used CB:39491 on CFL and it works great.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43397 )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43397/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43397/1//COMMIT_MSG@7 PS1, Line 7: FSPT FSP-T
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43397 )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/fspcar.c:
https://review.coreboot.org/c/coreboot/+/43397/1/src/soc/intel/skylake/bootb... PS1, Line 26: CONFIG_ROM_SIZE
I used CB:39491 on CFL and it works great.
Cool. Will apply it here.
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43397?usp=email )
Change subject: soc/intel/skylake: Add necessary FSPT params when FSP CAR is used ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Michał Żygowski (Code Review)
-
Patrick Rudolph (Code Review)
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Stefan Reinauer (Code Review)