Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Sridhar Siricilla, Kane Chen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )
Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ......................................................................
Patch Set 4: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63293/comment/74f8bd19_91c8f151 PS3, Line 11: informatrion
information
Done
Patchset:
PS2:
@subrata, as per Intel doc#723158, when extern VR is used, then reported issue may not occur. […]
I read in CB:63294 that the issue can result in display flicker, which seems to be completely unrelated to USB2 PHY power gating. I'd appreciate if you could add information about the issue in the commit message and in the comment for the option. This way, if someone else experiences the same issue, it's more likely that they'll notice the USB2 PHY power gating option and try enabling it.
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63293/comment/3e14efcd_588bfe06 PS4, Line 571: Enable I'd use `Disable` instead, given the option's name
https://review.coreboot.org/c/coreboot/+/63293/comment/616c0636_24828fca PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. I feel this is redundant. I'd rather mention *why* one would want to enable this option (AIUI, to prevent possible display flicker).
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Angel Pons (Code Review)