Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30961
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
mb/ocp/wedge100s: Add SuperIO support
* Enable COM1, COM2, PMC1 and PMC2
TODO: Look at additional configuration and EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb 2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30961/1
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index ce9c097..6224340 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_UART_8250IO + select SUPERIO_ITE_IT8528E
config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb index 3d66d0d..bbea89e 100644 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ b/src/mainboard/ocp/wedge100s/devicetree.cb @@ -11,6 +11,39 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end + chip superio/ite/it8528e + # COM1, routed to COM-e header + device pnp 6e.1 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + # COM2, routed to COM-e header + device pnp 6e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 6e.4 off end + device pnp 6e.5 off end + device pnp 6e.6 off end + device pnp 6e.a off end + device pnp 6e.f off end + device pnp 6e.10 off end + device pnp 6e.11 on + io 0x60 = 0x62 + io 0x62 = 0x66 + irq 0x70 = 1 + end + device pnp 6e.12 on + io 0x60 = 0x68 + io 0x62 = 0x6c + irq 0x70 = 1 + end + device pnp 6e.13 off end + device pnp 6e.14 off end + device pnp 6e.17 off end + device pnp 6e.18 off end + device pnp 6e.19 off end + end #superio/ite/it8528e end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
Patch Set 1: Code-Review+2
Hello Felix Held, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30961
to look at the new patch set (#3).
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
mb/ocp/wedge100s: Add SuperIO support
* Enable COM1, COM2, PMC1 and PMC2
TODO: Look at additional configuration and EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb 2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30961/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/30961/4/src/mainboard/ocp/wedge100s/Kconfig File src/mainboard/ocp/wedge100s/Kconfig:
https://review.coreboot.org/#/c/30961/4/src/mainboard/ocp/wedge100s/Kconfig@... PS4, Line 12: select SUPERIO_ITE_COMMON_PRE_RAM remove this one as it is selected here: https://review.coreboot.org/#/c/coreboot/+/30957/6/src/superio/ite/it8528e/K...
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
Patch Set 4: -Code-Review
Please address Elyes' comment; then I'll +2 it again
Hello Felix Held, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30961
to look at the new patch set (#5).
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
mb/ocp/wedge100s: Add SuperIO support
* Enable COM1, COM2, PMC1 and PMC2
TODO: Look at additional configuration and EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb 2 files changed, 34 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30961/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30961/4/src/mainboard/ocp/wedge100s/Kconfig File src/mainboard/ocp/wedge100s/Kconfig:
https://review.coreboot.org/#/c/30961/4/src/mainboard/ocp/wedge100s/Kconfig@... PS4, Line 12: select SUPERIO_ITE_COMMON_PRE_RAM
remove this one as it is selected here: https://review.coreboot. […]
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
Patch Set 5: Code-Review+2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
Patch Set 5: Code-Review+2
Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30961 )
Change subject: mb/ocp/wedge100s: Add SuperIO support ......................................................................
mb/ocp/wedge100s: Add SuperIO support
* Enable COM1, COM2, PMC1 and PMC2
TODO: Look at additional configuration and EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/30961 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb 2 files changed, 34 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved HAOUAS Elyes: Looks good to me, approved
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index ce9c097..bd5e665 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -9,13 +9,13 @@ select TSC_MONOTONIC_TIMER select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE - select SUPERIO_ITE_COMMON_PRE_RAM select FSP_EHCI1_ENABLE select MRC_CACHE_FMAP select ENABLE_FSP_FAST_BOOT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_UART_8250IO + select SUPERIO_ITE_IT8528E
config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb index 3d66d0d..bbea89e 100644 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ b/src/mainboard/ocp/wedge100s/devicetree.cb @@ -11,6 +11,39 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end + chip superio/ite/it8528e + # COM1, routed to COM-e header + device pnp 6e.1 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + # COM2, routed to COM-e header + device pnp 6e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 6e.4 off end + device pnp 6e.5 off end + device pnp 6e.6 off end + device pnp 6e.a off end + device pnp 6e.f off end + device pnp 6e.10 off end + device pnp 6e.11 on + io 0x60 = 0x62 + io 0x62 = 0x66 + irq 0x70 = 1 + end + device pnp 6e.12 on + io 0x60 = 0x68 + io 0x62 = 0x6c + irq 0x70 = 1 + end + device pnp 6e.13 off end + device pnp 6e.14 off end + device pnp 6e.17 off end + device pnp 6e.18 off end + device pnp 6e.19 off end + end #superio/ite/it8528e end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller
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Felix Held (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Rudolph (Code Review)