Change in coreboot[master]: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask skl, cnl & icl soc code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl R src/soc/intel/common/block/acpi/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl 21 files changed, 21 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/1
diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index f3e216d..49919d8 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -48,7 +48,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 8a43784..65c7be2 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -49,7 +49,7 @@ #endif
// Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 5ffdf18..4d2c4bf 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -54,7 +54,7 @@ #endif
/* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index a705457..bf207b7 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 03df2b9..112673c 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index af5f99d..6fe0cbd 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -49,7 +49,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 344e4a7..fd3df6e 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -52,10 +52,10 @@ #endif
/* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
- /* Low power idle table */ - #include <soc/intel/cannonlake/acpi/lpit.asl> + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 34862df..dd02606 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -55,7 +55,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 22e283f..5cfde62 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -54,7 +54,7 @@ #endif
/* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
/* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 5f4a349..4b7454c 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -45,6 +45,6 @@ #endif
// Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
} diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index c5f1136..952f345 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -45,6 +45,6 @@ #endif
// Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
} diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 15890f1..c84e41a 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -60,7 +60,7 @@ #endif
// Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 8a16551..83db423 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -57,7 +57,7 @@ #endif
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index af5f99d..6fe0cbd 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -49,7 +49,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index ac929a6..eb053b1 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -43,7 +43,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 1bf202e..14525d7 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -44,7 +44,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index e110067..72184eb 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -43,7 +43,7 @@
} // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index ac929a6..eb053b1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -43,7 +43,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <soc/intel/common/block/acpi/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/soc/intel/cannonlake/acpi/sleepstates.asl b/src/soc/intel/common/block/acpi/acpi/sleepstates.asl similarity index 94% rename from src/soc/intel/cannonlake/acpi/sleepstates.asl rename to src/soc/intel/common/block/acpi/acpi/sleepstates.asl index 2a351b6..1ab0e68 100644 --- a/src/soc/intel/cannonlake/acpi/sleepstates.asl +++ b/src/soc/intel/common/block/acpi/acpi/sleepstates.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2019 Intel Corp. * * * This program is free software; you can redistribute it and/or modify diff --git a/src/soc/intel/icelake/acpi/sleepstates.asl b/src/soc/intel/icelake/acpi/sleepstates.asl deleted file mode 100644 index 13cc358..0000000 --- a/src/soc/intel/icelake/acpi/sleepstates.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/soc/intel/skylake/acpi/sleepstates.asl deleted file mode 100644 index 905a3e2..0000000 --- a/src/soc/intel/skylake/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/36463/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36463/1//COMMIT_MSG@12 PS1, Line 12: : TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify : S0/S3/S4/S5 entries after booting to OS. It should even result in identical binaries. You can compare the hashes when build with BUILD_TIMELESS=1. That might speed up testing.
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... PS1, Line 17: : Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) : Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) : Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) : Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) Those have been the same for a very long time on Intel targets? Maybe move it to southbridge/intel/common/acpi (I don't care that much though where it ends ) and replace
southbridge/intel/i82801gx/acpi/sleepstates.asl southbridge/intel/bd82x6x/acpi/sleepstates.asl southbridge/intel/i82801ix/acpi/sleepstates.asl southbridge/intel/lynxpoint/acpi/sleepstates.asl southbridge/intel/fsp_rangeley/acpi/sleepstates.asl southbridge/intel/i82801jx/acpi/sleepstates.asl soc/intel/baytrail/acpi/sleepstates.asl soc/intel/fsp_baytrail/acpi/sleepstates.asl soc/intel/apollolake/acpi/sleepstates.asl soc/intel/braswell/acpi/sleepstates.asl soc/intel/broadwell/acpi/sleepstates.asl soc/intel/cannonlake/acpi/sleepstates.asl soc/intel/denverton_ns/acpi/sleepstates.asl soc/intel/skylake/acpi/sleepstates.asl soc/intel/icelake/acpi/sleepstates.asl\
Make sure to make the _S3 entry depend on HAVE_ACPI_RESUME with CPP.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... PS1, Line 17: : Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) : Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) : Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) : Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
Those have been the same for a very long time on Intel targets?
yes true, but my problem is that, not very comfortable keeping code changes without testing on real HW. hence limited to latest platforms since SKL. is that reasonable for now ?
Maybe move it to southbridge/intel/common/acpi (I don't care that much though where it ends ) and replace
Please feel free to move those platform as well if you think so.
southbridge/intel/i82801gx/acpi/sleepstates.asl southbridge/intel/bd82x6x/acpi/sleepstates.asl southbridge/intel/i82801ix/acpi/sleepstates.asl southbridge/intel/lynxpoint/acpi/sleepstates.asl southbridge/intel/fsp_rangeley/acpi/sleepstates.asl southbridge/intel/i82801jx/acpi/sleepstates.asl soc/intel/baytrail/acpi/sleepstates.asl soc/intel/fsp_baytrail/acpi/sleepstates.asl soc/intel/apollolake/acpi/sleepstates.asl soc/intel/braswell/acpi/sleepstates.asl soc/intel/broadwell/acpi/sleepstates.asl soc/intel/cannonlake/acpi/sleepstates.asl soc/intel/denverton_ns/acpi/sleepstates.asl soc/intel/skylake/acpi/sleepstates.asl soc/intel/icelake/acpi/sleepstates.asl\
Make sure to make the _S3 entry depend on HAVE_ACPI_RESUME with CPP.
yes, i missed this, will add
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36463
to look at the new patch set (#2).
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask skl, cnl & icl soc code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl R src/soc/intel/common/block/acpi/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl 21 files changed, 24 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... PS1, Line 17: : Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) : Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) : Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) : Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
Those have been the same for a very long time on Intel targets?
yes true, but my problem is that, not very comfortable keeping code changes without testing on real HW. hence limited to latest platforms since SKL. is that reasonable for now ?
I understand that, but in this case it's really identical code and the result should even be identical binaries if build with BUILD_TIMELESS=1.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{cnl,icl,skl}: Move sleepstates.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/1/src/soc/intel/common/block/... PS1, Line 17: : Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) : Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) : Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) : Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 })
Those have been the same for a very long time on Intel targets? […]
got it, let me do that.
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36463
to look at the new patch set (#3).
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and ask all IA CPU/SOC code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5gc-mx/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/foxconn/d41s/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/getac/p470/dsdt.asl M src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/ibase/mb899/dsdt.asl M src/mainboard/intel/apollolake_rvp/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/d510mo/dsdt.asl M src/mainboard/intel/d945gclf/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/986lcd-m/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/portwell/m107/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/roda/rk886ex/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl M src/mainboard/up/squared/dsdt.asl D src/soc/intel/apollolake/acpi/sleepstates.asl D src/soc/intel/baytrail/acpi/sleepstates.asl D src/soc/intel/braswell/acpi/sleepstates.asl D src/soc/intel/broadwell/acpi/sleepstates.asl D src/soc/intel/cannonlake/acpi/sleepstates.asl D src/soc/intel/denverton_ns/acpi/sleepstates.asl D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl D src/southbridge/intel/bd82x6x/acpi/sleepstates.asl R src/southbridge/intel/common/acpi/sleepstates.asl D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl D src/southbridge/intel/i82801gx/acpi/sleepstates.asl D src/southbridge/intel/i82801jx/acpi/sleepstates.asl D src/southbridge/intel/lynxpoint/acpi/sleepstates.asl 134 files changed, 127 insertions(+), 430 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/3
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36463/1//COMMIT_MSG@12 PS1, Line 12: : TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify : S0/S3/S4/S5 entries after booting to OS.
It should even result in identical binaries. […]
Done
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 3:
Patch Set 3:
(1 comment)
For Portwell M107 you'r adding S1 support. Any reason for this?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 3:
(1 comment)
For Portwell M107 you'r adding S1 support. Any reason for this?
#if !CONFIG(HAVE_ACPI_RESUME) Name(_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(_S3, Package(){0x5,0x0,0x0,0x0}) #endif
so you mean on portwell
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Frans Hendriks, Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Alexander Couzens, Evgeny Zinoviev, Werner Zeh, Vanny E, Huang Jin, Philipp Deppenwiese, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36463
to look at the new patch set (#4).
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and ask all IA CPU/SOC code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5gc-mx/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/foxconn/d41s/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/getac/p470/dsdt.asl M src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/ibase/mb899/dsdt.asl M src/mainboard/intel/apollolake_rvp/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/d510mo/dsdt.asl M src/mainboard/intel/d945gclf/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/986lcd-m/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/roda/rk886ex/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl M src/mainboard/up/squared/dsdt.asl D src/soc/intel/apollolake/acpi/sleepstates.asl D src/soc/intel/baytrail/acpi/sleepstates.asl D src/soc/intel/braswell/acpi/sleepstates.asl D src/soc/intel/broadwell/acpi/sleepstates.asl D src/soc/intel/cannonlake/acpi/sleepstates.asl D src/soc/intel/denverton_ns/acpi/sleepstates.asl D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl D src/southbridge/intel/bd82x6x/acpi/sleepstates.asl R src/southbridge/intel/common/acpi/sleepstates.asl D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl D src/southbridge/intel/i82801gx/acpi/sleepstates.asl D src/southbridge/intel/i82801jx/acpi/sleepstates.asl D src/southbridge/intel/lynxpoint/acpi/sleepstates.asl 133 files changed, 126 insertions(+), 429 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 4:
Patch Set 3:
Patch Set 3:
Patch Set 3:
(1 comment)
For Portwell M107 you'r adding S1 support. Any reason for this?
#if !CONFIG(HAVE_ACPI_RESUME) Name(_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(_S3, Package(){0x5,0x0,0x0,0x0}) #endif
so you mean on portwell
sorry that might be by mistake, fixed now
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 4: Code-Review+1
Works fine on Intel CoffeeLake RVP
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Thank you for doing this.
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... PS4, Line 9: , or : * (at your option) any later version. I guess there is nothing really copyrightable about this file, so I don't think the copyright header change is ok here? Let's not bikeshed on this...
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... PS4, Line 9: , or : * (at your option) any later version.
I guess there is nothing really copyrightable about this file, so I don't think the copyright header […]
oh yes, let me keep the original one here, makes more sense
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Frans Hendriks, Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Alexander Couzens, Evgeny Zinoviev, Werner Zeh, Vanny E, Huang Jin, Lean Sheng Tan, Philipp Deppenwiese, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36463
to look at the new patch set (#5).
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and ask all IA CPU/SOC code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5gc-mx/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/foxconn/d41s/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/getac/p470/dsdt.asl M src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/ibase/mb899/dsdt.asl M src/mainboard/intel/apollolake_rvp/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/d510mo/dsdt.asl M src/mainboard/intel/d945gclf/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/986lcd-m/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/roda/rk886ex/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl M src/mainboard/up/squared/dsdt.asl D src/soc/intel/apollolake/acpi/sleepstates.asl D src/soc/intel/baytrail/acpi/sleepstates.asl D src/soc/intel/braswell/acpi/sleepstates.asl D src/soc/intel/broadwell/acpi/sleepstates.asl D src/soc/intel/cannonlake/acpi/sleepstates.asl D src/soc/intel/denverton_ns/acpi/sleepstates.asl D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl D src/southbridge/intel/bd82x6x/acpi/sleepstates.asl R src/southbridge/intel/common/acpi/sleepstates.asl D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl D src/southbridge/intel/i82801gx/acpi/sleepstates.asl D src/southbridge/intel/i82801jx/acpi/sleepstates.asl D src/southbridge/intel/lynxpoint/acpi/sleepstates.asl 133 files changed, 120 insertions(+), 424 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/5
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 5: Code-Review+1
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Frans Hendriks, Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Alexander Couzens, Evgeny Zinoviev, Werner Zeh, Vanny E, Huang Jin, Lean Sheng Tan, Philipp Deppenwiese, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36463
to look at the new patch set (#6).
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and ask all IA CPU/SOC code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5gc-mx/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/foxconn/d41s/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/getac/p470/dsdt.asl M src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/ibase/mb899/dsdt.asl M src/mainboard/intel/apollolake_rvp/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/d510mo/dsdt.asl M src/mainboard/intel/d945gclf/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/986lcd-m/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/roda/rk886ex/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl M src/mainboard/up/squared/dsdt.asl D src/soc/intel/apollolake/acpi/sleepstates.asl D src/soc/intel/baytrail/acpi/sleepstates.asl D src/soc/intel/braswell/acpi/sleepstates.asl D src/soc/intel/broadwell/acpi/sleepstates.asl D src/soc/intel/cannonlake/acpi/sleepstates.asl D src/soc/intel/denverton_ns/acpi/sleepstates.asl D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl D src/southbridge/intel/bd82x6x/acpi/sleepstates.asl R src/southbridge/intel/common/acpi/sleepstates.asl D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl D src/southbridge/intel/i82801gx/acpi/sleepstates.asl D src/southbridge/intel/i82801jx/acpi/sleepstates.asl D src/southbridge/intel/lynxpoint/acpi/sleepstates.asl 134 files changed, 121 insertions(+), 425 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/6
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 7: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... PS4, Line 9: , or : * (at your option) any later version.
oh yes, let me keep the original one here, makes more sense
Well, when there is nothing copyrightable here (full ACK), why not remove the whole header like it's done for config and devicetree files?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... PS4, Line 9: , or : * (at your option) any later version.
Well, when there is nothing copyrightable here (full ACK), why not remove the whole header like it's done for config and devicetree files?
Coreboot lint check blocks that (iirc) and I don't think there is a linter out that that is smart enough to figure out if code is sufficiently original to be considered an original work, so it's fine just keeping it.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/36463/4/src/southbridge/intel/commo... PS4, Line 9: , or : * (at your option) any later version.
Well, when there is nothing copyrightable here (full ACK), why not remove the whole header like it […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 7:
(1 comment)
Maybe the ACPI sleepstates are more generic than originally thought?
https://review.coreboot.org/c/coreboot/+/36463/7/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/dsdt.asl:
PS7: Uhm, isn't Kahlee using AMD chips?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/7/src/mainboard/google/kahlee... File src/mainboard/google/kahlee/dsdt.asl:
PS7:
Uhm, isn't Kahlee using AMD chips?
oh yes. my bad. thanks
Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Michael Niewöhner, Frans Hendriks, Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Alexander Couzens, Evgeny Zinoviev, Werner Zeh, Vanny E, Huang Jin, Lean Sheng Tan, Philipp Deppenwiese, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36463
to look at the new patch set (#8).
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5gc-mx/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/foxconn/d41s/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/getac/p470/dsdt.asl M src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/ibase/mb899/dsdt.asl M src/mainboard/intel/apollolake_rvp/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/d510mo/dsdt.asl M src/mainboard/intel/d945gclf/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/986lcd-m/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/roda/rk886ex/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl M src/mainboard/up/squared/dsdt.asl D src/soc/intel/apollolake/acpi/sleepstates.asl D src/soc/intel/baytrail/acpi/sleepstates.asl D src/soc/intel/braswell/acpi/sleepstates.asl D src/soc/intel/broadwell/acpi/sleepstates.asl D src/soc/intel/cannonlake/acpi/sleepstates.asl D src/soc/intel/denverton_ns/acpi/sleepstates.asl D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl D src/southbridge/intel/bd82x6x/acpi/sleepstates.asl R src/southbridge/intel/common/acpi/sleepstates.asl D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl D src/southbridge/intel/i82801gx/acpi/sleepstates.asl D src/southbridge/intel/i82801jx/acpi/sleepstates.asl D src/southbridge/intel/lynxpoint/acpi/sleepstates.asl 133 files changed, 120 insertions(+), 424 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36463/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
Patch Set 7:
(1 comment)
Maybe the ACPI sleepstates are more generic than originally thought?
I just checked: the AMD common sleepstates.asl is different from Intel's, so reusing is not really doable.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
Patch Set 9:
Patch Set 7:
(1 comment)
Maybe the ACPI sleepstates are more generic than originally thought?
I just checked: the AMD common sleepstates.asl is different from Intel's, so reusing is not really doable.
i have reverted that mistake ?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36463/9/src/soc/intel/apollolake/ac... File src/soc/intel/apollolake/acpi/sleepstates.asl:
PS9: APL didn't have ACPI S4 here, does it work now?
https://review.coreboot.org/c/coreboot/+/36463/9/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl:
PS9: Rangeley says it does not support S1 nor S3 sleep states, has it been addressed?
Not that it's too critical, I don't think there are many Rangeley users and I think FSP 1.0 has problems with S3 sleep/resume anyway.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9: Code-Review+2
Patch Set 9:
Patch Set 9:
Patch Set 7:
(1 comment)
Maybe the ACPI sleepstates are more generic than originally thought?
I just checked: the AMD common sleepstates.asl is different from Intel's, so reusing is not really doable.
i have reverted that mistake ?
Yes, it is correct now. Thanks!
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36463/9/src/soc/intel/apollolake/ac... File src/soc/intel/apollolake/acpi/sleepstates.asl:
PS9:
APL didn't have ACPI S4 here, does it work now?
just adding in .asl code might not make it work. this might be maximum capabilities that bios can list but finally its OS which decide what all sleep state to support.
So no issue observed in APL device
https://review.coreboot.org/c/coreboot/+/36463/9/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl:
PS9:
Rangeley says it does not support S1 nor S3 sleep states, has it been addressed? […]
i have mentioned in APL comment
just adding in .asl code might not make it work. this might be maximum capabilities that bios can list but finally its OS which decide what all sleep state to support.
We are also testing on Rangley will wait for complete test results before merging
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36463/9/src/soc/intel/apollolake/ac... File src/soc/intel/apollolake/acpi/sleepstates.asl:
PS9:
just adding in .asl code might not make it work. […]
Done
https://review.coreboot.org/c/coreboot/+/36463/9/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl:
PS9:
i have mentioned in APL comment […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36463/9//COMMIT_MSG@7 PS9, Line 7: southbridge/intel/common/acpi I find this really odd. All recent Intel chipsets seem to use common code from soc/intel/common. And now these chipsets will have 2 common locations?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36463/9//COMMIT_MSG@7 PS9, Line 7: southbridge/intel/common/acpi
I find this really odd. All recent Intel chipsets seem to use common code from soc/intel/common. And now these chipsets will have 2 common locations?
I don't think this is bad. southbridge/intel/common is well maintained and other targets in intel/soc/ use it too. Besides there already are more common locations than soc/intel/common, e.g. cpu/intel/common.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36463/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36463/9//COMMIT_MSG@7 PS9, Line 7: southbridge/intel/common/acpi
I find this really odd. All recent Intel chipsets seem to use common code from soc/intel/common. […]
this CL is touching more than SOC present inside soc/intel/common hence had to add this file from southbridge/intel/common/acpi common to include both IA soc and cpu
btw, we are not selecting southbridge_common Kconfig from newer soc so i don;t we are actually using common definitions like RTC, VNVS etc
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36463 )
Change subject: soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi ......................................................................
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbook21/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asrock/h110m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p5gc-mx/dsdt.asl M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/foxconn/d41s/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/getac/p470/dsdt.asl M src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/hp/z220_sff_workstation/dsdt.asl M src/mainboard/ibase/mb899/dsdt.asl M src/mainboard/intel/apollolake_rvp/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/d510mo/dsdt.asl M src/mainboard/intel/d945gclf/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/strago/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/986lcd-m/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/t60/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/lenovo/x60/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/razer/blade_stealth_kbl/dsdt.asl M src/mainboard/roda/rk886ex/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M src/mainboard/supermicro/x11-lga1151-series/dsdt.asl M src/mainboard/up/squared/dsdt.asl D src/soc/intel/apollolake/acpi/sleepstates.asl D src/soc/intel/baytrail/acpi/sleepstates.asl D src/soc/intel/braswell/acpi/sleepstates.asl D src/soc/intel/broadwell/acpi/sleepstates.asl D src/soc/intel/cannonlake/acpi/sleepstates.asl D src/soc/intel/denverton_ns/acpi/sleepstates.asl D src/soc/intel/fsp_baytrail/acpi/sleepstates.asl D src/soc/intel/icelake/acpi/sleepstates.asl D src/soc/intel/skylake/acpi/sleepstates.asl D src/southbridge/intel/bd82x6x/acpi/sleepstates.asl R src/southbridge/intel/common/acpi/sleepstates.asl D src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl D src/southbridge/intel/i82801gx/acpi/sleepstates.asl D src/southbridge/intel/i82801jx/acpi/sleepstates.asl D src/southbridge/intel/lynxpoint/acpi/sleepstates.asl 133 files changed, 120 insertions(+), 424 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/adi/rcc-dff/dsdt.asl b/src/mainboard/adi/rcc-dff/dsdt.asl index 310ad04..e5cd0ea 100644 --- a/src/mainboard/adi/rcc-dff/dsdt.asl +++ b/src/mainboard/adi/rcc-dff/dsdt.asl @@ -49,5 +49,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 830c0c8..40af217 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -46,5 +46,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 65ce63e..641b951 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -30,7 +30,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 467a001..0025626 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -33,7 +33,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index 002dfca..e0e3a3a 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index f3e216d..0b3baf6 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -48,7 +48,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index f76c393..67088fd 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -27,7 +27,7 @@ #include "acpi/platform.asl" #include <southbridge/intel/lynxpoint/acpi/platform.asl> #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (_SB) diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 8452191..0e1cc3a 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -30,7 +30,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Device (_SB.PCI0) { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index e3abc26..c5f92e2 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -28,7 +28,7 @@ #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index 7b6bdf8..66f0efe 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -50,5 +50,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index 5ec7c19..cc9efbb 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index 002dfca..e0e3a3a 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index e3abc26..c5f92e2 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -28,7 +28,7 @@ #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index d9861ef..4b48e1f 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -32,7 +32,7 @@
/* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 89ad30c..1c7a620 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Device (_SB.PCI0) { diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index ad0940c..97df937 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -33,7 +33,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl index 3719154..bea6af7 100644 --- a/src/mainboard/esd/atom15/dsdt.asl +++ b/src/mainboard/esd/atom15/dsdt.asl @@ -48,7 +48,7 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index 8dc1194..dc1dacc 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index 002dfca..e0e3a3a 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 4471ef2..4e75968 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -55,5 +55,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index 95ed8d9..afc5386 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -50,5 +50,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index c00ee30..387fd32 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -30,7 +30,7 @@ #include <cpu/intel/common/acpi/cpu.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index 002dfca..e0e3a3a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index dbf8c96..7ee12a0 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -35,7 +35,7 @@
/* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Device (_SB.PCI0) { diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 7a2aad9..9a5dcc7 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -51,7 +51,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 41f908f..7b369d8 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -53,5 +53,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index dd18e95..c71535c 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -54,5 +54,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 3afdaaa..7aa62f8 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -62,7 +62,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index ab0b977..d5c709e 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -49,7 +49,7 @@ #endif
// Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..91d3704 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -54,7 +54,7 @@ #endif
/* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index a705457..3e9d570 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 03df2b9..44d544c 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index af5f99d..6dab56e 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -49,7 +49,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e2959a7..9329b58 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -52,10 +52,10 @@ #endif
/* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Low power idle table */ - #include <soc/intel/cannonlake/acpi/lpit.asl> + /* Low power idle table */ + #include <soc/intel/cannonlake/acpi/lpit.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index e216b13..add675d 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -51,7 +51,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index ce4ba91..e380f3e 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -55,5 +55,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index b434948..2b6c33f 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -45,7 +45,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index e866e21..1f72a6d 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -55,5 +55,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 34862df..7e0eb9a 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -55,7 +55,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 8ca9dfb..2393830 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -48,7 +48,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 2b2f522..29b8165 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -45,7 +45,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 58e0704..743a2f0 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -54,7 +54,7 @@ #endif
/* Chipset specific sleep states */ - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ #include <soc/intel/cannonlake/acpi/lpit.asl> diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 8424c25..6c45ea9 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -64,5 +64,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 1361a51..43d0fff 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -55,5 +55,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/hp/2570p/dsdt.asl b/src/mainboard/hp/2570p/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/2570p/dsdt.asl +++ b/src/mainboard/hp/2570p/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/2760p/dsdt.asl +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/8460p/dsdt.asl b/src/mainboard/hp/8460p/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/8460p/dsdt.asl +++ b/src/mainboard/hp/8460p/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/8470p/dsdt.asl b/src/mainboard/hp/8470p/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/8470p/dsdt.asl +++ b/src/mainboard/hp/8470p/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/8770w/dsdt.asl +++ b/src/mainboard/hp/8770w/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index ef67ee7..c3453b0 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/folio_9470m/dsdt.asl b/src/mainboard/hp/folio_9470m/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/folio_9470m/dsdt.asl +++ b/src/mainboard/hp/folio_9470m/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/revolve_810_g1/dsdt.asl b/src/mainboard/hp/revolve_810_g1/dsdt.asl index 756516e..7a171ae 100644 --- a/src/mainboard/hp/revolve_810_g1/dsdt.asl +++ b/src/mainboard/hp/revolve_810_g1/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index ef67ee7..c3453b0 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -32,7 +32,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index cc56d89..31b67a7 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -47,5 +47,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 2e3fa7a..9dd8879 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -33,6 +33,6 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
} diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index c713330..28d743e 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -52,5 +52,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/bayleybay_fsp/dsdt.asl b/src/mainboard/intel/bayleybay_fsp/dsdt.asl index 3719154..bea6af7 100644 --- a/src/mainboard/intel/bayleybay_fsp/dsdt.asl +++ b/src/mainboard/intel/bayleybay_fsp/dsdt.asl @@ -48,7 +48,7 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c719d23..acc4c7c 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -45,6 +45,6 @@ #endif
// Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
} diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 70d0bd6..f830035 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -45,6 +45,6 @@ #endif
// Chipset specific sleep states - #include <soc/intel/cannonlake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
} diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 8dc1194..dc1dacc 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 95ed8d9..afc5386 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -50,5 +50,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 60f4c74..9d1d261 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -30,7 +30,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 002dfca..e0e3a3a 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 911dcee..75073ca 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 45968fb..d9792ff 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -53,5 +53,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 759d669..d7711be 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -45,7 +45,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 9bc42cf..2636df1 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -50,5 +50,5 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/denverton_ns/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index ad469fa..6657a6e 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -60,7 +60,7 @@ #endif
// Chipset specific sleep states - #include <soc/intel/icelake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 8a16551..059bcd5 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -57,7 +57,7 @@ #endif
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index af5f99d..6dab56e 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -49,7 +49,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index 48b24b9..6fccf49 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -39,5 +39,5 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index 310ad04..e5cd0ea 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -49,5 +49,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index 48b24b9..6fccf49 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -39,5 +39,5 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl index 3719154..bea6af7 100644 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -48,7 +48,7 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index 310ad04..e5cd0ea 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -49,5 +49,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index ac929a6..86ea299 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -43,7 +43,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 5052ba26..e89b887 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -58,7 +58,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 42fd7ea..ef3e231 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -53,7 +53,7 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states - #include <soc/intel/broadwell/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index c412c4e..d4ffd7b 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -46,5 +46,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index f0dd7ee..33ef834 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index ecd8f27..815600d 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -33,7 +33,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index cc9b7aa..4e5737b 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -32,7 +32,7 @@ #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 6aafec6..eb9c2ad 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -53,7 +53,7 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Hybrid graphics support code */ #include "acpi/graphics.asl" diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index afc9b3e..5c99f1b 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -87,7 +87,7 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Dock support code */ #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 48e0076..7e80a6f 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -37,7 +37,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 3014a57..82358aa 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -35,7 +35,7 @@ #include <southbridge/intel/lynxpoint/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Device (_SB.PCI0) { diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 8f8c47d..1292321 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -59,7 +59,7 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index 002dfca..e0e3a3a 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -38,5 +38,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 3e5ede5..5fd1c9d 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -41,7 +41,7 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// Chipset specific sleep states - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5a..4d1281e 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 8a11ec1..e300234 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -52,7 +52,7 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Dock support code */ #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index afc9b3e..5c99f1b 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -87,7 +87,7 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Dock support code */ #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 1cb4add..83bf8c4 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -52,5 +52,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 2bba47c..00430bb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -53,7 +53,7 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 8808539..d3e3602 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -30,7 +30,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Device (_SB.PCI0) { diff --git a/src/mainboard/opencellular/rotundu/dsdt.asl b/src/mainboard/opencellular/rotundu/dsdt.asl index 3719154..bea6af7 100644 --- a/src/mainboard/opencellular/rotundu/dsdt.asl +++ b/src/mainboard/opencellular/rotundu/dsdt.asl @@ -48,7 +48,7 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index 3bf7fbd..e84f525 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -81,5 +81,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index bd49349..3cd4ef9 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -41,7 +41,7 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/broadwell/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 1bf202e..1cd0531 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -44,7 +44,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index e110067..0112654 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -43,7 +43,7 @@
} // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index d332874..f9a2abe 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -51,5 +51,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index f930a14..e8fb13d 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -53,5 +53,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index 859b4cd..21ab369 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -50,5 +50,5 @@ }
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index c007432..e6bbed7 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -56,5 +56,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 969ef66..7029106 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -53,5 +53,5 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 60ba44b..67eca4a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -33,7 +33,7 @@ #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index 9bc42cf..2636df1 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -50,5 +50,5 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/denverton_ns/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index 9ce3ef8..449bcf8 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -42,5 +42,5 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/siemens/mc_tcu3/dsdt.asl b/src/mainboard/siemens/mc_tcu3/dsdt.asl index 3719154..bea6af7 100644 --- a/src/mainboard/siemens/mc_tcu3/dsdt.asl +++ b/src/mainboard/siemens/mc_tcu3/dsdt.asl @@ -48,7 +48,7 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 3a587b6..6ed19ee 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -21,7 +21,7 @@ #include "acpi/platform.asl" #include <southbridge/intel/lynxpoint/acpi/platform.asl> #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> #include <cpu/intel/common/acpi/cpu.asl>
Device (_SB.PCI0) diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index ac929a6..86ea299 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -43,7 +43,7 @@ }
// Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific #include "acpi/mainboard.asl" diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl index 48b24b9..6fccf49 100644 --- a/src/mainboard/up/squared/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -39,5 +39,5 @@ }
/* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/soc/intel/apollolake/acpi/sleepstates.asl b/src/soc/intel/apollolake/acpi/sleepstates.asl deleted file mode 100644 index e79f2f0..0000000 --- a/src/soc/intel/apollolake/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/baytrail/acpi/sleepstates.asl b/src/soc/intel/baytrail/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3..0000000 --- a/src/soc/intel/baytrail/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(_S1, Package(){0x1,0x1,0x0,0x0}) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl deleted file mode 100644 index d37f9cc..0000000 --- a/src/soc/intel/braswell/acpi/sleepstates.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/broadwell/acpi/sleepstates.asl b/src/soc/intel/broadwell/acpi/sleepstates.asl deleted file mode 100644 index 585da9e..0000000 --- a/src/soc/intel/broadwell/acpi/sleepstates.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S1, Package () { 0x1, 0x1, 0x0, 0x0 }) -Name (_S2, Package () { 0x1, 0x1, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/cannonlake/acpi/sleepstates.asl b/src/soc/intel/cannonlake/acpi/sleepstates.asl deleted file mode 100644 index 2a351b6..0000000 --- a/src/soc/intel/cannonlake/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017-2018 Intel Corp. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/denverton_ns/acpi/sleepstates.asl b/src/soc/intel/denverton_ns/acpi/sleepstates.asl deleted file mode 100644 index 7da8413..0000000 --- a/src/soc/intel/denverton_ns/acpi/sleepstates.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 - 2009 coresystems GmbH - * Copyright (C) 2014 - 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -//Name(_S1, Package(){0x1,0x1,0x0,0x0}) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl deleted file mode 100644 index 8e47f5c..0000000 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(_S1, Package(){0x1,0x1,0x0,0x0}) -#if CONFIG(HAVE_ACPI_RESUME) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -#endif -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/icelake/acpi/sleepstates.asl b/src/soc/intel/icelake/acpi/sleepstates.asl deleted file mode 100644 index 13cc358..0000000 --- a/src/soc/intel/icelake/acpi/sleepstates.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/soc/intel/skylake/acpi/sleepstates.asl deleted file mode 100644 index 905a3e2..0000000 --- a/src/soc/intel/skylake/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) -Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) -Name (_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) -Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl b/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3..0000000 --- a/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(_S1, Package(){0x1,0x1,0x0,0x0}) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl similarity index 100% rename from src/southbridge/intel/i82801ix/acpi/sleepstates.asl rename to src/southbridge/intel/common/acpi/sleepstates.asl diff --git a/src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl b/src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl deleted file mode 100644 index cd391fb..0000000 --- a/src/southbridge/intel/fsp_rangeley/acpi/sleepstates.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) - -/* - * S1 and S3 sleep states are not supported - * Name(_S1, Package(){0x1,0x1,0x0,0x0}) - * Name(_S3, Package(){0x5,0x5,0x0,0x0}) - */ - -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3..0000000 --- a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(_S1, Package(){0x1,0x1,0x0,0x0}) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl deleted file mode 100644 index 79818a1..0000000 --- a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -#if !CONFIG(HAVE_ACPI_RESUME) -Name(_S1, Package(){0x1,0x0,0x0,0x0}) -#else -Name(_S3, Package(){0x5,0x0,0x0,0x0}) -#endif -Name(_S4, Package(){0x6,0x0,0x0,0x0}) -Name(_S5, Package(){0x7,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/lynxpoint/acpi/sleepstates.asl b/src/southbridge/intel/lynxpoint/acpi/sleepstates.asl deleted file mode 100644 index 4d1d0b3..0000000 --- a/src/southbridge/intel/lynxpoint/acpi/sleepstates.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(_S1, Package(){0x1,0x1,0x0,0x0}) -Name(_S3, Package(){0x5,0x5,0x0,0x0}) -Name(_S4, Package(){0x6,0x6,0x0,0x0}) -Name(_S5, Package(){0x7,0x7,0x0,0x0})
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Frans Hendriks (Code Review)
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Furquan Shaikh (Code Review)
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Lean Sheng Tan (Code Review)
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Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)