Attention is currently required from: Ravi Kumar Bokka, Hung-Te Lin, Nico Huber, Tim Wawrzynczak, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu, Jianjun Wang.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )
Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
From Qualcomm's reply, 1MB is max possible PCIe endpoints. […]
Hi Yu-ping, Tim and I have a meeting scheduled with Qualcomm Tuesday to discuss this, so hopefully we can resolve this issue and unblock you guys. Sorry for the delay. I will post an update after the meeting.
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