New patch to review for coreboot: northbridge/amd/pi: Add support for soldered down memory
Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10672
-gerrit
commit 35498fd2cacfe13b6b8db9386fa8c3c34bb75f04 Author: Dave Frodin dave.frodin@se-eng.com Date: Wed May 20 10:33:51 2015 -0600
northbridge/amd/pi: Add support for soldered down memory
This adds support for binarypi based boards that have soldered down memory but no SPD EEPROM onboard. A PlatformMemoryConfiguration[] table that describes the memory configuration must be defined in the mainboard folder. An example table is also included in the comments.
Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/northbridge/amd/pi/agesawrapper.c | 118 ++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+)
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 255b31d..ccd5526 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -27,6 +27,30 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h>
+#if (IS_ENABLED(CONFIG_SPD_CACHE)) + /* + * For systems that have soldered down memory but do not have a soldered + * down SPD EEPROM that describes that memory the mainboard code must + * provide a PlatformMemoryConfiguration[] table that describes the + * memory configuration. An example table is shown below in the comments + * of agesawrapper_amdinitpost(). + * + * This table would also be needed for boards that route the memory clocks + * differently than the clocks for the AMD reference design. This could + * include boards with either DIMMS/SODIMMs, or soldered down memory with + * a SPD EEPROM. + * + * In addition to adding the PlatformMemoryConfiguration table these + * changes are also needed: + * 1) CONFIG_SPD_CACHE must me selected in the mainboards Kconfig. + * 2) In the mainboards BiosCallOuts.c file AGESA_READ_SPD must point + * to the agesa_ReadSpd_from_cbfs function rather than agesa_ReadSpd. + * 3) A spd.bin file needs to be generated and added to CBFS. + */ +#include <PlatformMemoryConfiguration.h> +extern const PSO_ENTRY PlatformMemoryConfiguration[]; +#endif + VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -136,6 +160,100 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+#if (IS_ENABLED(CONFIG_SPD_CACHE)) + /* + * Add the memory configuration table needed for soldered down memory + * + * const PSO_ENTRY PlatformMemoryConfiguration[] = { + * // + * // The following macros are supported (use comma to separate macros): + * // + * // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + * // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + * // AGESA will base on this value to disable unused MemClk to save power. + * // Example: + * // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + * // Bit AM3/S1g3 pin name + * // 0 M[B,A]_CLK_H/L[0] + * // 1 M[B,A]_CLK_H/L[1] + * // 2 M[B,A]_CLK_H/L[2] + * // 3 M[B,A]_CLK_H/L[3] + * // 4 M[B,A]_CLK_H/L[4] + * // 5 M[B,A]_CLK_H/L[5] + * // 6 M[B,A]_CLK_H/L[6] + * // 7 M[B,A]_CLK_H/L[7] + * // And platform has the following routing: + * // CS0 M[B,A]_CLK_H/L[4] + * // CS1 M[B,A]_CLK_H/L[2] + * // CS2 M[B,A]_CLK_H/L[3] + * // CS3 M[B,A]_CLK_H/L[5] + * // Then platform can specify the following macro: + * // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + * // + * // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + * // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + * // AGESA will base on this value to tristate unused CKE to save power. + * // + * // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + * // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + * // AGESA will base on this value to tristate unused ODT pins to save power. + * // + * // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + * // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + * // AGESA will base on this value to tristate unused Chip select to save power. + * // + * // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + * // Specifies the number of DIMM slots per channel. + * // + * // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + * // Specifies the number of Chip selects per channel. + * // + * // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + * // Specifies the number of channels per socket. + * // + * // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + * // Specifies DDR bus speed of channel ChannelID on socket SocketID. + * // + * // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + * // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + * // + * // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * // Byte6Seed, Byte7Seed, ByteEccSeed) + * // Specifies the write leveling seed for a channel of a socket. + * // + * // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * // Byte6Seed, Byte7Seed, ByteEccSeed) + * // Speicifes the HW RXEN training seed for a channel of a socket + * // + * + * #define SEED_WL 0x0E + * WRITE_LEVELING_SEED( + * ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + * SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL, + * SEED_WL), + * + * #define SEED_A 0x12 + * HW_RXEN_SEED( + * ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + * SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + * SEED_A), + * + * NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + * NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + * MOTHER_BOARD_LAYERS (LAYERS_6), + * + * MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + * CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + * ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + * CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + * + * PSO_END + * }; + */ + + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration; +#endif // (IS_ENABLED(CONFIG_SPD_CACHE)) + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
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Dave Frodin