Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47257 )
Change subject: soc/intel/common/block/cse: Clear post code before reset ......................................................................
soc/intel/common/block/cse: Clear post code before reset
To avoid "unknown post code 0x55" entries in the event log on cold boot clear the post code before doing the CSE initiated reset.
Signed-off-by: Duncan Laurie dlaurie@google.com Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47257/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef6db3d..d10492b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -555,6 +555,9 @@ { uint32_t csr;
+ /* Clear post code to prevent eventlog entry from unknown code. */ + post_code(0); + /* Send reset request */ csr = read_host_csr(); csr |= (CSR_RESET | CSR_IG);
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47257 )
Change subject: soc/intel/common/block/cse: Clear post code before reset ......................................................................
Patch Set 1: Code-Review+2
heh thanks for fixing that, it was bugging me 😊
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47257 )
Change subject: soc/intel/common/block/cse: Clear post code before reset ......................................................................
Patch Set 3: Code-Review+2
Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47257 )
Change subject: soc/intel/common/block/cse: Clear post code before reset ......................................................................
soc/intel/common/block/cse: Clear post code before reset
To avoid "unknown post code 0x55" entries in the event log on cold boot clear the post code before doing the CSE initiated reset.
Signed-off-by: Duncan Laurie dlaurie@google.com Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef6db3d..d10492b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -555,6 +555,9 @@ { uint32_t csr;
+ /* Clear post code to prevent eventlog entry from unknown code. */ + post_code(0); + /* Send reset request */ csr = read_host_csr(); csr |= (CSR_RESET | CSR_IG);
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
-
Tim Wawrzynczak (Code Review)