[S] Change in coreboot[main]: WIP: arch/riscv: add test to set variable for menvcfg

[ron minnich (Code Review)]

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug.

Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81293?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: WIP: arch/riscv: add test to set variable for menvcfg
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WIP: arch/riscv: add test to set variable for menvcfg

there are many variant features on SoCs.

This CL demonstrates a simple way to test feature existence
with low effort.

It correctly detects the menvcfg register.

Signed-off-by: Ronald G Minnich

Change-Id: If9f5db74d7467ab00044d20050531bcb511cce39
---
M src/arch/riscv/include/arch/encoding.h
M src/arch/riscv/payload.c
M src/arch/riscv/ramstage.S
3 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/81293/2