[S] Change in coreboot[main]: soc/intel/xeon_sp: Make NUMA support by default

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81439?usp=email )

Change subject: soc/intel/xeon_sp: Make NUMA support by default
......................................................................

soc/intel/xeon_sp: Make NUMA support by default

TEST=Build and boot on intel/archercity CRB

Change-Id: I84f07c16e24e441a885144df8c805f1310acae29
Signed-off-by: Shuo Liu 
Co-authored-by: Ziang Wang 
Co-authored-by: Gang Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81439
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/numa.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/uncore.c
5 files changed, 21 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk
index f4051ea..18a53ac 100644
--- a/src/soc/intel/xeon_sp/Makefile.mk
+++ b/src/soc/intel/xeon_sp/Makefile.mk
@@ -11,9 +11,10 @@
 romstage-y += ../../../cpu/intel/car/romstage.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c
 ramstage-y += memmap.c pch.c lockdown.c finalize.c
+ramstage-y += numa.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
-ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c
+ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c
 smm-y += smihandler.c pmutil.c
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 2d6005b..3472d58 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -136,3 +136,8 @@
 {
    return true;
 }
+
+uint8_t get_cxl_node_count(void)
+{
+	return 0;
+}
diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c
index 62657dc..0186865 100644
--- a/src/soc/intel/xeon_sp/numa.c
+++ b/src/soc/intel/xeon_sp/numa.c
@@ -50,7 +50,6 @@

/* Fill in processor domains */
    uint8_t i, j, socket;
-	struct device *dev;
    for (socket = 0, i = 0; i < num_sockets; socket++) {
    	if (!soc_cpu_is_enabled(socket))
    		continue;
@@ -73,6 +72,7 @@
    if (num_cxlnodes == 0)
    	return;

+#if CONFIG(SOC_INTEL_HAS_CXL)
    /* There are CXL nodes, fill in generic initiator domain after the processors pds */
    uint8_t skt_id, cxl_id;
    const CXL_NODE_SOCKET *cxl_hob = get_cxl_node();
@@ -83,7 +83,7 @@
    		pds.pds[i].socket_bitmap = node.SocketBitmap;
    		pds.pds[i].base = node.Address;
    		pds.pds[i].size = node.Size;
-			dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0);
+			struct device *dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0);
    		pds.pds[i].dev = dev;
    		pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds);
    		if (!pds.pds[i].distances)
@@ -97,6 +97,7 @@
    		}
    	}
    }
+#endif
 }

/*
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 6f48246..0ccacfb 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -209,3 +209,8 @@
 {
    return true;
 }
+
+uint8_t get_cxl_node_count(void)
+{
+	return 0;
+}
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index a177a89..e4c4675 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -338,14 +338,12 @@
 {
    int index = 0;

-	if (CONFIG(SOC_INTEL_HAS_CXL)) {
-		static bool once;
-		if (!once) {
-			/* Construct NUMA data structure. This is needed for CXL. */
-			fill_pds();
-			dump_pds();
-			once = true;
-		}
+	static bool once;
+	if (!once) {
+		/* Construct NUMA data structure. This is needed for CXL. */
+		fill_pds();
+		dump_pds();
+		once = true;
    }

/* Read standard PCI resources. */