[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache

[Jérémy Compostella (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun.

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
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Patch Set 9:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81212/comment/b54464bd_399eb56c :
PS6, Line 42:  2 MB
> I think this is a step in the right direction. Both AMD FSP code and Intel APL/GLK code uses a static addr for FSP-M. They should be moved to this solution if possible?

I do think this is good idea. However I do not have access to any of those board currently and I am going to be out for about 2 month (April 1st - June 14th) so it will have to wait. But this is not urgent.

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/81212/comment/2bbf9669_fef39c80 :
PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE
> > Having an assertion can avoid the device to run into the actual issue but I don't  see an option a […]

Done

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/81212/comment/57533ef0_5af787bc :
PS8, Line 229: It requires the PRERAM_CBFS_CACHE_SIZE to be large enough to
             : 	  accommodate the entire FSP-M binary and therefore the SoC to
             : 	  support a large enough Cache-As-RAM (DCACHE_RAM_SIZE).
             :
> The commit message says something about needing adjustments for this to work. […]

Done