Change in coreboot[master]: mb/google/hatch/var/jinlon: Update DPTF parameters

[Chen Wisley (Code Review)]

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

mb/google/hatch/var/jinlon: Update DPTF parameters

The change applies the DPTF parameters.

BUG=none
TEST=build and verified by thermal team.

Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen 
---
M src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 94 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37832/1

diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
index f1f0943..74195e1 100644
--- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
@@ -13,4 +13,96 @@
  * GNU General Public License for more details.
  */

-#include <baseboard/acpi/dptf.asl>
+#define DPTF_CPU_PASSIVE	70
+#define DPTF_CPU_CRITICAL	105
+#define DPTF_CPU_ACTIVE_AC0	70
+#define DPTF_CPU_ACTIVE_AC1	65
+#define DPTF_CPU_ACTIVE_AC2	60
+#define DPTF_CPU_ACTIVE_AC3	50
+#define DPTF_CPU_ACTIVE_AC4	40
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
+#define DPTF_TSR0_PASSIVE	62
+#define DPTF_TSR0_CRITICAL	105
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Thermal Sensor 2"
+#define DPTF_TSR1_PASSIVE	54
+#define DPTF_TSR1_CRITICAL	105
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+})
+
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {67,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {60,		0xFFFFFFFF,	3838,	90,	900},
+	Package () {50,		0xFFFFFFFF,	2904,	55,	550},
+	Package () {40,		0xFFFFFFFF,	2337,	30,	300},
+	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
+	Package () {10,		0xFFFFFFFF,	800,	10,	100},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.TCPU, 100, 70, 67, 60, 50, 40, 0, 0,
+			0, 0, 0
+	},
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on Ambient (TSR0) */
+	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+
+	/* Charger Throttle Effect on Charger (TSR1) */
+	Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		12000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		51000,	/* PowerLimitMinimum */
+		51000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index 28b18b8..223fd1b 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -1,4 +1,5 @@
 chip soc/intel/cannonlake
+	register "tdp_pl2_override" = "51"

register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,

[Chen Wisley (Code Review)]

Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 2:

This change is ready for review.

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG@9 
PS2, Line 9: The change applies the DPTF parameters.
Who gave you these parameters?

[Chen Wisley (Code Review)]

Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG@9 
PS2, Line 9: The change applies the DPTF parameters.
> Who gave you these parameters?

Hi Paul,
  our thermal team provided the setting data
thanks

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG@9 
PS2, Line 9: The change applies the DPTF parameters.
Maybe:
> Apply DPTF parameters received from the thermal team.

[Chen Wisley (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37832

to look at the new patch set (#3).

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

mb/google/hatch/var/jinlon: Update DPTF parameters

The change applies the DPTF parameters received from the thermal team.

BUG=b:146540028
TEST=build and verified by thermal team.

Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen 
---
M src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 94 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37832/3

[Chen Wisley (Code Review)]

Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37832/2//COMMIT_MSG@9 
PS2, Line 9: The change applies the DPTF parameters.
> Maybe: […]

Done

[Paul Fagerburg (Code Review)]

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 3: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37832/3/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/37832/3/src/mainboard/google/hatch/... 
PS3, Line 2: 	register "tdp_pl2_override" = "51"
How about adding PL1 override here too?  tdp_pl1_override = "15", as indicated in dptf.asl above?

[Chen Wisley (Code Review)]

Hello Paul Fagerburg, Philip Chen, Tim Wawrzynczak, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37832

to look at the new patch set (#4).

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

mb/google/hatch/var/jinlon: Update DPTF parameters

The change applies the DPTF parameters received from the thermal team.

BUG=b:146540028
TEST=build and verified by thermal team.

Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen 
---
M src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 95 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37832/4

[Chen Wisley (Code Review)]

Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37832/3/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/37832/3/src/mainboard/google/hatch/... 
PS3, Line 2: 	register "tdp_pl2_override" = "51"
> How about adding PL1 override here too?  tdp_pl1_override = "15", as indicated in dptf. […]

Done

[Paul Fagerburg (Code Review)]

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 4: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

Patch Set 4: Code-Review+2

I'm assuming these aren't the final parameters either, so LGTM

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37832 )

Change subject: mb/google/hatch/var/jinlon: Update DPTF parameters
......................................................................

mb/google/hatch/var/jinlon: Update DPTF parameters

The change applies the DPTF parameters received from the thermal team.

BUG=b:146540028
TEST=build and verified by thermal team.

Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Fagerburg 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 95 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Paul Fagerburg: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
index f1f0943..74195e1 100644
--- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
@@ -13,4 +13,96 @@
  * GNU General Public License for more details.
  */

-#include <baseboard/acpi/dptf.asl>
+#define DPTF_CPU_PASSIVE	70
+#define DPTF_CPU_CRITICAL	105
+#define DPTF_CPU_ACTIVE_AC0	70
+#define DPTF_CPU_ACTIVE_AC1	65
+#define DPTF_CPU_ACTIVE_AC2	60
+#define DPTF_CPU_ACTIVE_AC3	50
+#define DPTF_CPU_ACTIVE_AC4	40
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
+#define DPTF_TSR0_PASSIVE	62
+#define DPTF_TSR0_CRITICAL	105
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Thermal Sensor 2"
+#define DPTF_TSR1_PASSIVE	54
+#define DPTF_TSR1_CRITICAL	105
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+})
+
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {67,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {60,		0xFFFFFFFF,	3838,	90,	900},
+	Package () {50,		0xFFFFFFFF,	2904,	55,	550},
+	Package () {40,		0xFFFFFFFF,	2337,	30,	300},
+	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
+	Package () {10,		0xFFFFFFFF,	800,	10,	100},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.TCPU, 100, 70, 67, 60, 50, 40, 0, 0,
+			0, 0, 0
+	},
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on Ambient (TSR0) */
+	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+
+	/* Charger Throttle Effect on Charger (TSR1) */
+	Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		12000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		51000,	/* PowerLimitMinimum */
+		51000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		32000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index fd2861e..c9613d2 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -1,4 +1,6 @@
 chip soc/intel/cannonlake
+	register "tdp_pl1_override" = "15"
+	register "tdp_pl2_override" = "51"

register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,