Change in coreboot[master]: soc/intel/skylake: Override KBL-U/R IccMax settings

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/23060

Change subject: soc/intel/skylake: Override KBL-U/R IccMax settings
......................................................................

soc/intel/skylake: Override KBL-U/R IccMax settings

According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeroni/Pentium are different. This patch overrides the IccMax
settings for KBL-U/R since device tree could not handle all
of them and it is inefficient to maintain the same code for all
variants. Hence, place it in the common code so that all variants
could leverage the benefits.

+----------------+-------------+---------------+-------+-------+
| Domain/Setting |  SA         |  IA           | GTUS  |  GTS  |
+----------------+-------------+---------------+-------+-------+
| IccMax         | 6A(U42)     | 64A(U42)      | 31A   | 31A   |
|                | 4.5A(Others)| 29A(Celeron)  | 31A   | 31A   |
|                |             | 32A(i3/i5)    | 31A   | 31A   |
+----------------+-------------+---------------+-------+-------+

BUG=b:71369428
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42,
     KBL-U and Celeron SKUs are identified correctly and IccMax settings
     are passed to FSPS correctly.

Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/vr_config.c
3 files changed, 57 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/23060/1

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 24a239e..b1d882d 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -272,6 +272,14 @@
    for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
    	fill_vr_domain_config(params, i, &config->domain_vr_config[i]);

+	/*
+     * KBL-U/R CPUs are with a complicated setting matrix for IccMax
+     * that devicetree is unable to handle all of them with variants.
+     * Besides, it's inefficient to maintain the same code per variant.
+     * Hence, move the IccMax override to common code here.
+     */
+    override_kbl_ur_icc_max(params);
+
    /* Show SPI controller if enabled in devicetree.cb */
    dev = dev_find_slot(0, PCH_DEVFN_SPI);
    params->ShowSpiController = dev->enabled;
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index 66b4a01..1f948e2 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -98,4 +98,6 @@

void fill_vr_domain_config(void *params,
    		int domain, const struct vr_config *cfg);
+void override_kbl_ur_icc_max(void *params);
+
 #endif
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index cfbd796..3f6cbe5 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -14,10 +14,19 @@
  *
  */

+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
 #include <fsp/api.h>
 #include <soc/ramstage.h>
 #include <soc/vr_config.h>

+#define KBLR_ICCMAX_SA_I7_U42	6
+#define KBLU_ICCMAX_SA_U22	4.5
+#define KBLR_ICCMAX_CORE_I7_U42	64
+#define KBLU_ICCMAX_CORE_U22	32
+#define KBLU_ICCMAX_CORE_PENTIUM_CELERON	29
+
 /* Default values for domain configuration. PSI3 and PSI4 are disabled. */
 static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
    [VR_SYSTEM_AGENT] = {
@@ -84,6 +93,44 @@
    },
 };

+static uint16_t get_dev_id(device_t dev)
+{
+    return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+void override_kbl_ur_icc_max(void *params)
+{
+	FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
+	device_t dev = SA_DEV_ROOT;
+	uint16_t id = get_dev_id(dev);
+
+	/*
+	 * Iccmax table from Doc #55910 Section 7.2 DC Specifications, the
+	 * Iccmax is the samse among KBL-Y but KBL-U/R. This function will
+	 * identify device ID and set corresponding Iccmax values.
+	 * +----------------+-------------+---------------+-------+-------+
+	 * | Domain/Setting |  SA         |  IA           | GTUS  |  GTS  |
+	 * +----------------+-------------+---------------+-------+-------+
+	 * | IccMax         | 6A(U42)     | 64A(U42)      | 31A   | 31A   |
+	 * |                | 4.5A(Others)| 29A(P/C)      | 31A   | 31A   |
+	 * |                |             | 32A(i3/i5)    | 31A   | 31A   |
+	 * +----------------+-------------+---------------+-------+-------+
+	 */
+
+	if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) { /* KBL 4+2 SKU */
+		vr_params->IccMax[VR_SYSTEM_AGENT] = VR_CFG_AMP(KBLR_ICCMAX_SA_I7_U42);
+		vr_params->IccMax[VR_IA_CORE] = VR_CFG_AMP(KBLR_ICCMAX_CORE_I7_U42);
+	} else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) {
+		dev = PCH_DEV_LPC;
+		id = get_dev_id(dev);
+		if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22)	/* Pentium or Celeron SKU */
+			vr_params->IccMax[VR_IA_CORE] = VR_CFG_AMP(KBLU_ICCMAX_CORE_PENTIUM_CELERON);
+		else	/* KBL 2+2 SKU */
+			vr_params->IccMax[VR_IA_CORE] = VR_CFG_AMP(KBLU_ICCMAX_CORE_U22);
+		/* The IccMax of SA is the same for i3/i5/Celeron and Pentium */
+		vr_params->IccMax[VR_SYSTEM_AGENT] = VR_CFG_AMP(KBLU_ICCMAX_SA_U22);
+	}
+}
 void fill_vr_domain_config(void *params,
    	int domain, const struct vr_config *chip_cfg)
 {