Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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soc/intel/alderlake: Correct TCSS XHCI Port status offset

The patch corrects TCSS XHCI Port status offset. The information is
captured from the ADL-P Processor EDS Volume 2b of 2(DOC ID:619502).

BUG=None
TEST=Verified boot on Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59
---
M src/soc/intel/alderlake/xhci.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/55230/1

diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c
index 9226336..c2a4654 100644
--- a/src/soc/intel/alderlake/xhci.c
+++ b/src/soc/intel/alderlake/xhci.c
@@ -15,7 +15,7 @@
 #define PCH_XHCI_USB3_PORT_NUM		4

#define TCSS_XHCI_USB2_PORT_STATUS_REG	0x480
-#define TCSS_XHCI_USB3_PORT_STATUS_REG	0x540
+#define TCSS_XHCI_USB3_PORT_STATUS_REG	0x490
 #define TCSS_XHCI_USB2_PORT_NUM		10
 #define TCSS_XHCI_USB3_PORT_NUM		4