Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36553 )
Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 41:
remove space
Done
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 226: : Name (EP_B, 0) /* to store EP BAR */ : Name (MH_B, 0) /* to store MCH BAR */ : Name (PC_B, 0) /* to store PCIe BAR */ : Name (PC_L, 0) /* to store PCIe BAR Length */ : Name (DM_B, 0) /* to store DMI BAR
Why cache it?
to avoid multiple read if any ?
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 310: LASH range
memory mapped part of FLASH
Done
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 311: FIOH
Is it referenced somewhere? You can maybe drop it? It's not really a PCI resource either?
Done
https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/acp... PS2, Line 314: LIOH
not referenced?
Done