Change in coreboot[master]: soc/amd/common: Refactor single GPIO programming

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42691 )

Change subject: soc/amd/common: Refactor single GPIO programming
......................................................................

soc/amd/common: Refactor single GPIO programming

Make it clearer all the GPIO bank register programming
parameters originate from the same soc_amd_gpio entry.

Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42691
Reviewed-by: Felix Held 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 13 insertions(+), 20 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index ebd74e0..af948ce 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -181,31 +181,24 @@

__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {}

-static void set_single_gpio(const struct soc_amd_gpio *gpio_list_ptr,
+static void set_single_gpio(const struct soc_amd_gpio *g,
    		    struct sci_trigger_regs *sci_trigger_cfg)
 {
-	uint32_t control, control_flags;
-	uint8_t mux, gpio;
    static const struct soc_amd_event *gev_tbl;
    static size_t gev_items;
    int gevent_num;
    const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
    		ENV_SEPARATE_VERSTAGE);

-	gpio = gpio_list_ptr->gpio;
-	mux = gpio_list_ptr->function;
-	control = gpio_list_ptr->control;
-	control_flags = gpio_list_ptr->flags;
+	iomux_write8(g->gpio, g->function & AMD_GPIO_MUX_MASK);
+	iomux_read8(g->gpio); /* Flush posted write */

-	iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK);
-	iomux_read8(gpio); /* Flush posted write */
+	soc_gpio_hook(g->gpio, g->function);

-	soc_gpio_hook(gpio, mux);
-
-	gpio_setbits32(gpio, PAD_CFG_MASK, control);
+	gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control);
    /* Clear interrupt and wake status (write 1-to-clear bits) */
-	gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS);
-	if (control_flags == 0)
+	gpio_or32(g->gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS);
+	if (g->flags == 0)
    	return;

/* Can't set SMI flags from PSP */
@@ -215,17 +208,17 @@
    if (gev_tbl == NULL)
    	soc_get_gpio_event_table(&gev_tbl, &gev_items);

-	gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items);
+	gevent_num = get_gpio_gevent(g->gpio, gev_tbl, gev_items);
    if (gevent_num < 0) {
    	printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n",
-				     gpio);
+				     g->gpio);
    	return;
    }

-	if (control_flags & GPIO_FLAG_SMI) {
-		program_smi(control_flags, gevent_num);
-	} else if (control_flags & GPIO_FLAG_SCI) {
-		fill_sci_trigger(control_flags, gevent_num, sci_trigger_cfg);
+	if (g->flags & GPIO_FLAG_SMI) {
+		program_smi(g->flags, gevent_num);
+	} else if (g->flags & GPIO_FLAG_SCI) {
+		fill_sci_trigger(g->flags, gevent_num, sci_trigger_cfg);
    	soc_route_sci(gevent_num);
    }
 }