Change in coreboot[master]: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 148 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42225/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3fcf50a..b77b189 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -75,10 +75,6 @@ int default 64
-config VERSTAGE_ADDR - hex - default 0x4000000 - config VGA_BIOS_ID string default "1002,15d8" @@ -399,4 +395,46 @@ Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD.
+config VERSTAGE_ADDR + hex + depends on VBOOT_STARTS_IN_BOOTBLOCK + default 0x4000000 + +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +config RWA_REGION_ONLY + string + default "apu/amdfw_a" + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "apu/amdfw_b" + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + +#TODO: Change this to get the positions from fmap +config PICASSO_FW_A_POSITION + hex + help + Location of the AMD firmware in the RW_A region + +config PICASSO_FW_B_POSITION + hex + help + Location of the AMD firmware in the RW_B region + +endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b8c865f..d80713c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -232,6 +232,19 @@ PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin
+# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +# Place SHAREDMEM immediately below the 4KB boundary below the reset vector. +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +_PSP_SHAREDMEM_BASE=$(call int-subtract, $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) + 0x10) $(PSP_SHAREDMEM_SIZE)) 0x1000) +PSP_SHAREDMEM_BASE=$(shell printf "0x%x" $(_PSP_SHAREDMEM_BASE)) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +PSP_VERSTAGE_FILE=$(obj)/psp_verstage.bin +endif + # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28
@@ -274,6 +287,7 @@ OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage)
OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ @@ -295,6 +309,64 @@ OPT_PSP_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode) OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) + +AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + --apob-nv-size $(shell printf "0x%x" \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ + --apob-nv-base $(shell printf "0x%x" $(call int-add, \ + $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_PMUI_FILE1) \ + $(OPT_PSP_PMUI_FILE2) \ + $(OPT_PSP_PMUI_FILE3) \ + $(OPT_PSP_PMUI_FILE4) \ + $(OPT_PSP_PMUD_FILE1) \ + $(OPT_PSP_PMUD_FILE2) \ + $(OPT_PSP_PMUD_FILE3) \ + $(OPT_PSP_PMUD_FILE4) \ + $(OPT_PSP_UCODE_FILE1) \ + $(OPT_PSP_UCODE_FILE2) \ + $(OPT_PSP_UCODE_FILE3) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + --flashsize $(CONFIG_ROM_SIZE)
# Copy prebuild APCBs if they exist $(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin @@ -375,66 +447,16 @@ $(call_strip_quotes, $(PSP_S0I3_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ + $(PSP_VERSTAGE_FILE) \ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - --apob-nv-size $(shell printf "0x%x" \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ - --apob-nv-base $(shell printf "0x%x" $(call int-add, \ - $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_PSP_UCODE_FILE1) \ - $(OPT_PSP_UCODE_FILE2) \ - $(OPT_PSP_UCODE_FILE3) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ - $(OPT_SEC_DEBUG_FILE) \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ - --output $@ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @@ -442,6 +464,24 @@ $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE)
+$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_B_POSITION)) \ + --anywhere \ + --output $@ + ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw INTERMEDIATE+=add_amdfw @@ -467,6 +507,18 @@ apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw
+ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) +apu/amdfw_b-type := raw +endif + endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
Hello build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42225
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed --- M src/security/vboot/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 3 files changed, 133 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42225/2
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42225/3/src/security/vboot/Makefile... File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42225/3/src/security/vboot/Makefile... PS3, Line 169: # specified in the CONFIG_RW_REGION_ONLY are only placed in all RW regions. Files specified only placed or "are placed in all RW regions"?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42225/3/src/security/vboot/Makefile... File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42225/3/src/security/vboot/Makefile... PS3, Line 169: # specified in the CONFIG_RW_REGION_ONLY are only placed in all RW regions. Files specified
only placed or "are placed in all RW regions"?
Done
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42225
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 4 files changed, 149 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42225/4
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42225
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 4 files changed, 149 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42225/5
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42225/6/src/security/vboot/Makefile... File src/security/vboot/Makefile.inc:
PS6: Please split the security/vboot changes into their own CL.
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Kconfig... PS6, Line 506: depends on VBOOT_STARTS_IN_BOOTBLOCK We need the address so we can boot vboot without psp verstage.
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Makefil... PS6, Line 261: APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) Can you make the APOB cleanup it's own change.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42225/6/src/security/vboot/Makefile... File src/security/vboot/Makefile.inc:
PS6:
Please split the security/vboot changes into their own CL.
Done
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Kconfig... PS6, Line 506: depends on VBOOT_STARTS_IN_BOOTBLOCK
We need the address so we can boot vboot without psp verstage.
Done
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Makefil... PS6, Line 261: APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE)))
Can you make the APOB cleanup it's own change.
Done.
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42225
to look at the new patch set (#7).
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses.
TEST=Build & boot trembyle. See that we're booting from the correct region. BUG=b:158124527
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 114 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42225/7
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
Patch Set 7: Code-Review+2
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Makefil... File src/soc/amd/picasso/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/42225/6/src/soc/amd/picasso/Makefil... PS6, Line 261: APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE)))
Done.
Done
Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42225 )
Change subject: soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions ......................................................................
soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses.
TEST=Build & boot trembyle. See that we're booting from the correct region. BUG=b:158124527
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 114 insertions(+), 54 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5872a6f..4d07af6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -504,4 +504,32 @@ Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD.
+if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +config RWA_REGION_ONLY + string + default "apu/amdfw_a" + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "apu/amdfw_b" + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + +config PICASSO_FW_A_POSITION + hex + help + Location of the AMD firmware in the RW_A region + +config PICASSO_FW_B_POSITION + hex + help + Location of the AMD firmware in the RW_B region + +endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index dee65b5..e592f4a 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -314,6 +314,59 @@ OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size)
+AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + --apob-nv-size $(shell printf "0x%x" \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ + --apob-nv-base $(shell printf "0x%x" $(call int-add, \ + $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ + $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_PMUI_FILE1) \ + $(OPT_PSP_PMUI_FILE2) \ + $(OPT_PSP_PMUI_FILE3) \ + $(OPT_PSP_PMUI_FILE4) \ + $(OPT_PSP_PMUD_FILE1) \ + $(OPT_PSP_PMUD_FILE2) \ + $(OPT_PSP_PMUD_FILE3) \ + $(OPT_PSP_PMUD_FILE4) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + --flashsize $(CONFIG_ROM_SIZE) + # Copy prebuild APCBs if they exist $(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin cp $< $@ @@ -397,60 +450,9 @@ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - --apob-nv-size $(shell printf "0x%x" \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) \ - --apob-nv-base $(shell printf "0x%x" $(call int-add, \ - $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ - $(OPT_SEC_DEBUG_FILE) \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ - --output $@ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @@ -458,11 +460,41 @@ $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE)
+$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_B_POSITION)) \ + --anywhere \ + --output $@ + cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw
+ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) +apu/amdfw_b-type := raw +endif + $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
cpu_microcode_bins += $(wildcard 3rdparty/amd_blobs/picasso/PSP/UcodePatch_*.bin)
-
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Martin Roth (Code Review)
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