Change in coreboot[master]: soc/intel/alderlake: Enable Irms UPD for ADL

[Ronak Kanabar (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Kane Chen, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph.
Hello V Sowmya, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Vinay Kumar, Subrata Banik, Balaji Manigandan, Kane Chen, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/56330

to look at the new patch set (#14).

Change subject: soc/intel/alderlake: Enable Irms UPD for ADL
......................................................................

soc/intel/alderlake: Enable Irms UPD for ADL

This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.

This change also optimize the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.

BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs

Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/alderlake/vr_config.c
1 file changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/56330/14