CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44410 )
Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ......................................................................
soc/mediatek/mt8192: Add DRAM resource in ramstage
Add DRAM resource in ramstage to load payload.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/soc.c 2 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44410/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 25574c9..b0faf62 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -18,7 +18,9 @@ romstage-y += ../common/uart.c
ramstage-y += ../common/gpio.c gpio.c +ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c new file mode 100644 index 0000000..9850fa6 --- /dev/null +++ b/src/soc/mediatek/mt8192/soc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8192_ops = { + CHIP_NAME("SOC Mediatek MT8192") + .enable_dev = enable_soc_dev, +};
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44410 )
Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ......................................................................
Patch Set 1: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44410 )
Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ......................................................................
Patch Set 1: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44410 )
Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ......................................................................
soc/mediatek/mt8192: Add DRAM resource in ramstage
Add DRAM resource in ramstage to load payload.
Signed-off-by: CK Hu ck.hu@mediatek.com Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/soc.c 2 files changed, 31 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 25574c9..b0faf62 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -18,7 +18,9 @@ romstage-y += ../common/uart.c
ramstage-y += ../common/gpio.c gpio.c +ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c new file mode 100644 index 0000000..9850fa6 --- /dev/null +++ b/src/soc/mediatek/mt8192/soc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8192_ops = { + CHIP_NAME("SOC Mediatek MT8192") + .enable_dev = enable_soc_dev, +};
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44410 )
Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44410/2/src/soc/mediatek/mt8192/soc... File src/soc/mediatek/mt8192/soc.c:
https://review.coreboot.org/c/coreboot/+/44410/2/src/soc/mediatek/mt8192/soc... PS2, Line 5: #include <symbols.h> is this used ?
CK HU has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44410 )
Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44410/2/src/soc/mediatek/mt8192/soc... File src/soc/mediatek/mt8192/soc.c:
https://review.coreboot.org/c/coreboot/+/44410/2/src/soc/mediatek/mt8192/soc... PS2, Line 5: #include <symbols.h>
is this used ?
It's redundant. But this patch has been merged, so I would send another patch to remove this.
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CK HU (Code Review) -
HAOUAS Elyes (Code Review)
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Hung-Te Lin (Code Review)
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Yu-Ping Wu (Code Review)