[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely

[Johannes Hahn (Code Review)]

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh.

Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email )

Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
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Patch Set 3:

(2 comments)

Patchset:

PS3: 
Done.

Commit Message:

https://review.coreboot.org/c/coreboot/+/85606/comment/3255ebfa_306b4d94?usp... :
PS1, Line 14: This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`

Please fix.