Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph.
Hello build bot (Jenkins), Jamie Chen, Henry Sun, Tim Wawrzynczak, Angel Pons, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60009

to look at the new patch set (#17).

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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soc/intel/jasperlake: Add CdClock frequency config

Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.

BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang 
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/17