[S] Change in coreboot[main]: Kconfig: Place XIP components and FIT at high flash addresses

[Patrick Rudolph (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Shuo Liu, Tim Chu, Yu-Ping Wu.

Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email )

Change subject: Kconfig: Place XIP components and FIT at high flash addresses
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Patch Set 9:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86570/comment/713ff9b5_d4babccd?usp... :
PS8, Line 9: CACHE_ROM_SIZE
> Cache as ram working on non-evict mode, or in-another word, if contents are evicted, due to backend  […]

Still unclear how CAR has an influence on the cache setup. You write that using more than 16 MiB will evict cache lines from CAR? How is that possible when they are in non-evict mode?

GNR is not allowed to use more than 16MiB of what? Cache lines in non evict mode? Cache lines not in non evict mode? Combined cache lines in NEM and not in NEM?

It doesn't matter if your romstage/fspm.bin/... is at the upper or lower part of the SPI flash, it has always the same size and will always use the same amount of cache lines when the whole mmaped ROM is marked WP.