Change in coreboot[master]: soc/intel/icl: enable common CPU code

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 )

Change subject: soc/intel/icl: enable common CPU code
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Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/romst... 
File src/soc/intel/icelake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/45826/2/src/soc/intel/icelake/romst... 
PS2, Line 59: 	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
> Assuming 1) and VMX would be disabled. Wouldn't we need to call something […]

Ouch, now I know where the problem is... 2) is impossible with SkipMpInit=0. FSP always locks FC, for both VmxEnable=0 and =1. So without SkipMpInit=1, we only have option 1) left. No idea why I first thought "keep FSP from doing anything (VmxEnable=0)" :/