Patch set updated for coreboot: dda9b74 mainboard/jetway/nf81-t56n-lf: Init SIO HWM multi-func regs

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5500

-gerrit

commit dda9b74773d257ed4fc533add6a1de25ab87af50
Author: Edward O'Callaghan 
Date:   Sun Apr 13 22:31:08 2014 +1000

mainboard/jetway/nf81-t56n-lf: Init SIO HWM multi-func regs

The Fintek F71869AD found on this board needs special "Multifunction
    registers" to be tweaked before it will control the CPU fan properly.

Change-Id: I0b93c878b532bfa39b9ceb10ce6bada079408b6b
    Signed-off-by: Edward O'Callaghan 
---
 src/mainboard/jetway/nf81-t56n-lf/Makefile.inc  |   4 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c    |   6 ++
 src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c | 129 ++++++++++++++++++++++++
 src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h |  29 ++++++
 4 files changed, 166 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
index e1f18a9..2e9bd0c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
+++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
@@ -29,9 +29,9 @@ romstage-y += agesawrapper.c
 romstage-y += BiosCallOuts.c
 romstage-y += PlatformGnbPcie.c

+romstage-y += superio_hwm.c
+
 ramstage-y += buildOpts.c
 ramstage-y += agesawrapper.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
-
-
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 846d5c7..336dc17 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -19,6 +19,7 @@
  */

#include "agesawrapper.h"
+#include "superio_hwm.h"

#include <arch/cpu.h>
 #include <arch/io.h>
@@ -52,6 +53,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
 #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)

+#define HWM_DEV PNP_DEV(0x2e, F71869AD_HWM)
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
    u32 val;
@@ -79,6 +82,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    	console_init();
    }

+	/* Fintek F71869AD Hardware Monitor needs special configuration */
+	superio_enable_hwm(HWM_DEV);
+
    /* Halt if there was a built in self test failure */
    post_code(0x34);
    report_bist_failure(bist);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c
new file mode 100644
index 0000000..29b4786
--- /dev/null
+++ b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.c
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Just enough of a driver to make coreboot control system fans.
+ * No configuration is necessary for the OS to pick up the device.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+
+#include "superio_hwm.h"
+
+#define DEBUG_SUPERIO_HWM 0
+
+typedef struct superio_hwm_config {
+	u32 base;
+} hwm_config_t;
+
+static void write_index(u16 port, u8 reg, u8 value)
+{
+	outb(reg, port);
+	outb(value, port + 1);
+}
+
+static u8 read_index(u16 port, u8 reg)
+{
+	outb(reg, port);
+	return inb(port + 1);
+}
+
+static void init_hwm_registers(u16 base, u8 * hwm_reg_values, int size)
+{
+	u8 reg, value;
+	int i;
+
+	for (i = 0; i < size; i += 3) {
+		reg = hwm_reg_values[i];
+		value = read_index(base, reg);
+		value &= 0xff & hwm_reg_values[i + 1];
+		value |= 0xff & hwm_reg_values[i + 2];
+		printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, "
+		       "value = 0x%02x\n", base, reg, value);
+		write_index(base, reg, value);
+#if DEBUG_SUPERIO_HWM == 1
+		value = read_index(base, reg);
+		printk(BIOS_DEBUG, "Super I/O HWM (read back): base = 0x%04x, reg = 0x%02x, "
+		       "value = 0x%02x\n", base, reg, value);
+#endif /* DEBUG_SUPERIO_HWM */
+	}
+}
+
+/* Initialize F71869AD hardware monitor registers, usually at 0x225. */
+void superio_enable_hwm(device_t dev)
+{
+	hwm_config_t * config = dev->chip_info;
+
+	/* return if hwm is disabled in devicetree.cb */
+	if (!dev->enabled || !config)
+		return;
+
+	u32 hwm_base = config->base;
+
+	printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pnp %04x\n"
+		, hwm_base);
+
+	struct resource *res = find_resource(dev, PNP_IDX_IO0);
+	if (!res) {
+		printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base);
+	printk(BIOS_DEBUG, "Super I/O HWM: Configuring registers...\n");
+
+	/* Fintek F71869AD AMD mode HWM (ordered) programming sequence. */
+	u8 hwm_reg_values[] = {
+	/*  reg  mask  data */
+	0x08, 0x00, 0x98, /* SMBus Address p.53 */
+	0x0a, 0x00, 0x02, /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
+	/* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
+	0xaf, 0x00, 0x8c, /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
+	0x9f, 0x00, 0x8a, /* set FAN_PROG_SEL = 1 */
+	0x94, 0x00, 0x00, /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */
+	0x96, 0x00, 0x07, /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
+	0x95, 0x00, 0x33, /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */
+	0x9f, 0x00, 0x0a, /* set FAN_PROG_SEL = 0 */
+	/* .. */
+	0x02, 0x00, 0x30, /* OVT_MODE p.52 */
+	0x60, 0x00, 0x22, /* Temperature PME# Enable Register p.79 */
+	0x63, 0x00, 0x20, /* Temperature BEEP Enable Register p.58 */
+	0x64, 0x00, 0x22, /* T1 OVT and High Limit Temperature Select Register p.82 */
+	0x66, 0x00, 0x22, /* OVT and Alert Output Enable Register 1 p.59 */
+	0x82, 0x00, 0x76, /* Temperature sensors 1 OVT limit p.61 */
+	0x91, 0x00, 0x07, /* FAN Interrupt Status Register p.63 */
+	0x90, 0x00, 0x02, /* FAN PME# Enable Register p.85 */
+	0xa3, 0x00, 0x0e, /* FAN1 RPM mode p.70 */
+	0xa9, 0x00, 0x14, /* VT1 Boundary 2 Temperature p.71 */
+	0xaa, 0x00, 0xff, /* FAN1 Segment 1 Speed Count */
+	0xab, 0x00, 0x0e, /* FAN1 Segment 2 Speed Count */
+	0xae, 0x00, 0x07, /* FAN1 Segment 3 Speed Count */
+	/* .. */
+	0xee, 0x00, 0x01, /* SMB_Status p.83 */
+	0xed, 0x00, 0x01, /* SMB/TSI Command Byte p.83 */
+	0xef, 0x00, 0x82, /* SMB_Protocal p.83 */
+	};
+
+	init_hwm_registers(res->base, hwm_reg_values, ARRAY_SIZE(hwm_reg_values));
+}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h
new file mode 100644
index 0000000..012cb66
--- /dev/null
+++ b/src/mainboard/jetway/nf81-t56n-lf/superio_hwm.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_HWM_H
+#define SUPERIO_HWM_H
+
+#include <device/device.h>
+
+/* Initialize F71869AD hardware monitor registers, usually at 0x225. */
+void superio_enable_hwm(device_t);
+
+#endif /* SUPERIO_HWM_H */