[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC

[Philipp Hug (Code Review)]

Attention is currently required from: Maximilian Brune.

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/sifive/fu740: Add FU740 SOC
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Patch Set 10: Code-Review+1

(6 comments)

File src/soc/sifive/fu740/Kconfig:

https://review.coreboot.org/c/coreboot/+/76689/comment/724b2095_e03d2576 :
PS10, Line 28: # working HART uses U7 core
RISCV_WORKING_HARTID is set to 0, which is S7?

https://review.coreboot.org/c/coreboot/+/76689/comment/4aea5acd_9c9dd8bd :
PS10, Line 47: 	default 0 # use S7 core as default hart
deliberate use of S7 for coreboot?

File src/soc/sifive/fu740/clint.c:

https://review.coreboot.org/c/coreboot/+/76689/comment/42655258_d666286f :
PS10, Line 17: 	write32((void *)(FU740_CLINT + 4 * (uintptr_t)hartid), !!val);
use write32p?

File src/soc/sifive/fu740/gpio.c:

https://review.coreboot.org/c/coreboot/+/76689/comment/9e1a6cd4_dae2dfdf :
PS10, Line 33: 	uint32_t output_val = read32((void *)SIFIVE_GPIO_OUTPUT_VAL);
use read32p/write32p?

File src/soc/sifive/fu740/memlayout.ld:

https://review.coreboot.org/c/coreboot/+/76689/comment/b6c036f9_f0dcc5ea :
PS10, Line 22: 	//REGION(opensbi, FU740_DRAM, 256K, 4K)
comment not needed?

File src/soc/sifive/fu740/spi.c:

https://review.coreboot.org/c/coreboot/+/76689/comment/01d4332c_98ba2162 :
PS10, Line 186: 	//sckmode.raw_bits = 0;
why is this code commented here? delete it?