[L] Change in coreboot[main]: [WIP]soc/intel/xeon_sp: Use common _CRS code generation

[Arthur Heymans (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80796?usp=email )

Change subject: [WIP]soc/intel/xeon_sp: Use common _CRS code generation
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Patch Set 3:

(1 comment)

File src/soc/intel/xeon_sp/spr/soc_acpi.c:

https://review.coreboot.org/c/coreboot/+/80796/comment/a9ecfb98_7c95531b :
PS3, Line 78: /* For stack with CXL device, the PCIe bus resource is BusBase only. */
            : 		if (is_iio_cxl_stack_res(ri))
            : 			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
I had a very similar patchtrain to this one. CXL stacks are a problem... Should CXL domains devices be added too to the tree?