Change in coreboot[master]: drives/amd/agesa: remove legacy wrapper and separate CAR teardown
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
drives/amd/agesa: remove legacy wrapper and separate CAR teardown
TEST=boot PC Engines apu1
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I2ef73a2afa8dbb6ae676ee9fdc6beeecde57d6a5 --- M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/cache_as_ram.S A src/drivers/amd/agesa/exit_car.S 3 files changed, 47 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37171/1
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 4d5bd3e..1b0dd3e 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -13,32 +13,22 @@
ifeq ($(CONFIG_DRIVERS_AMD_PI),y)
-ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER),y) - -romstage-y += romstage.c -romstage-y += mtrr_fixme.c -romstage-y += state_machine.c - -ramstage-y += state_machine.c - cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -postcar-y += cache_as_ram.S - -else - -romstage-y += heapmanager.c - -endif
romstage-y += def_callouts.c romstage-y += eventlog.c +romstage-y += mtrr_fixme.c +romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c +romstage-y += romstage.c +romstage-y += state_machine.c
+postcar-y += exit_car.S + +ramstage-y += acpi_tables.c ramstage-y += def_callouts.c ramstage-y += eventlog.c ramstage-y += heapmanager.c -ramstage-y += acpi_tables.c - -romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c +ramstage-y += state_machine.c
endif diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index dcb0c43..1c53275 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,7 +27,6 @@
.code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end -.globl chipset_teardown_car
_cache_as_ram_setup:
@@ -105,59 +104,11 @@ pushl %eax call romstage_main
-#if CONFIG(POSTCAR_STAGE) - /* We do not return. Execution continues with run_postcar_phase() * calling to chipset_teardown_car below. */ jmp postcar_entry_failure
-chipset_teardown_car: - -/* - * Retrieve return address from stack as it will get trashed below if - * execution is utilizing the cache-as-ram stack. - */ - pop %esp - -#else - - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. */ - -#endif - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -/* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK - -#if CONFIG(POSTCAR_STAGE) - - jmp *%esp - -#else - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - -#endif - - /* Should never see this postcode */ - post_code(0xaf) - -stop: - hlt - jmp stop - /* These are here for linking purposes. */ .weak early_all_cores, romstage_main early_all_cores: @@ -165,6 +116,8 @@ postcar_entry_failure: /* Should never see this postcode */ post_code(0xae) +stop: + hlt jmp stop
_cache_as_ram_setup_end: diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S new file mode 100644 index 0000000..f9d056e --- /dev/null +++ b/src/drivers/amd/agesa/exit_car.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gcccar.inc> +#include <cpu/x86/cache.h> + +.code32 +.globl chipset_teardown_car + +chipset_teardown_car: + pop %esp + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + jmp *%esp
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
Michal, we need to get all the things on the same branch on gerrit.
Can you drop 'git log master..' so I know what you got there already.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
Patch Set 1:
Michal, we need to get all the things on the same branch on gerrit.
Can you drop 'git log master..' so I know what you got there already.
* ea53d244ea (HEAD -> master) northbridge/amd/pi: drop BINARYPI_LEGACY_WRAPPER * fa2dd4e2b9 drives/amd/agesa: remove legacy wrapper and separate CAR teardown * 2d52f08035 nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER * 1e989a5de0 northbridge/amd/pi: define the number of IOAPICs | * f3758b6738 (origin/master, origin/HEAD) AGESA,binaryPI: Move SCI enable outside table creation
Setting the same topic won't do?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Michal, we need to get all the things on the same branch on gerrit.
Can you drop 'git log master..' so I know what you got there already.
- ea53d244ea (HEAD -> master) northbridge/amd/pi: drop BINARYPI_LEGACY_WRAPPER
- fa2dd4e2b9 drives/amd/agesa: remove legacy wrapper and separate CAR teardown
- 2d52f08035 nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
- 1e989a5de0 northbridge/amd/pi: define the number of IOAPICs
| * f3758b6738 (origin/master, origin/HEAD) AGESA,binaryPI: Move SCI enable outside table creation
Setting the same topic won't do?
No, topic is nothing but a UI thing. There are some old Change-Ids that I want to bring back here.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Michal, we need to get all the things on the same branch on gerrit.
Can you drop 'git log master..' so I know what you got there already.
- ea53d244ea (HEAD -> master) northbridge/amd/pi: drop BINARYPI_LEGACY_WRAPPER
- fa2dd4e2b9 drives/amd/agesa: remove legacy wrapper and separate CAR teardown
- 2d52f08035 nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
- 1e989a5de0 northbridge/amd/pi: define the number of IOAPICs
| * f3758b6738 (origin/master, origin/HEAD) AGESA,binaryPI: Move SCI enable outside table creation
Setting the same topic won't do?
No, topic is nothing but a UI thing. There are some old Change-Ids that I want to bring back here.
Let me rebase things on one branch. I will take about 5 of your commits and 2 or 3 of my old cleanups from 2017. There might be some valuable commentary there with old Change-Ids.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Michal, we need to get all the things on the same branch on gerrit.
Can you drop 'git log master..' so I know what you got there already.
- ea53d244ea (HEAD -> master) northbridge/amd/pi: drop BINARYPI_LEGACY_WRAPPER
- fa2dd4e2b9 drives/amd/agesa: remove legacy wrapper and separate CAR teardown
- 2d52f08035 nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
- 1e989a5de0 northbridge/amd/pi: define the number of IOAPICs
| * f3758b6738 (origin/master, origin/HEAD) AGESA,binaryPI: Move SCI enable outside table creation
Setting the same topic won't do?
No, topic is nothing but a UI thing. There are some old Change-Ids that I want to bring back here.
Okay. So what is our starting point? I would like to avoid work duplication. I can go with binaryPI postcar and AGESA,binaryPI C bootblock on top of the change you will point me. I already got the postcar and C bootblock on apu2 working earlier. Please let me know about the course.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
src/cpu/amd/pi/Makefile.inc:cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
We cannot split the file until all binaryPI boards are at POSTCAR_STAGE (or disabled from build).
I will squash and submit this with CB:18526 Change-Id.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Patch Set 1:
Okay. So what is our starting point? I would like to avoid work duplication. I can go with binaryPI postcar and AGESA,binaryPI C bootblock on top of the change you will point me. I already got the postcar and C bootblock on apu2 working earlier. Please let me know about the course.
Work on the biosram and ap_entry, keeping in mind we should share the same implementation code with amd/stoneyridge on how APs behave in bootblock. Like done with FSP, I feel all AGESAv5 interface code should go under drivers/ because it gets obscure if cpu/amd/pi starts to build code from soc/amd/stoneyridge. Even more so, if cpu/amd/agesa does the same for C_ENV_BB feature.
I won't touch anything C_ENV_BB related until POSTCAR_STAGE for apu2 gets merged, so that's also orthogonal development so our works should not collide too bad.
Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37171 )
Change subject: drives/amd/agesa: remove legacy wrapper and separate CAR teardown ......................................................................
Abandoned
Another change is present with better approach
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)