Change in coreboot[master]: ec/google/chromeec: Add APIs for USB-C DP ALT mode

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57138 )

Change subject: ec/google/chromeec: Add APIs for USB-C DP ALT mode
......................................................................

ec/google/chromeec: Add APIs for USB-C DP ALT mode

Add API to allow AP to send the command to EC to enter DP ALT mode
and API to wait for DP HPD event.

BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build
coreboot and update your system. Boot the system you will find below
message in the coreboot log with or without USB-C display connected:
'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'.

Signed-off-by: Derek Huang 
Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Furquan Shaikh 
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
2 files changed, 54 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 9086693..5a8e4f6 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1508,6 +1508,33 @@
    return 0;
 }

+int google_chromeec_typec_control_enter_dp_mode(int port)
+{
+	if (!google_chromeec_check_feature(EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY))
+		return 0;
+
+	struct ec_params_typec_control typec_control = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_ENTER_MODE,
+		.mode_to_enter = TYPEC_MODE_DP,
+	};
+
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_TYPEC_CONTROL,
+		.cmd_version = 0,
+		.cmd_data_in = &typec_control,
+		.cmd_size_in = sizeof(typec_control),
+		.cmd_data_out = NULL,
+		.cmd_size_out = 0,
+		.cmd_dev_index = 0,
+	};
+
+	if (google_chromeec_command(&cmd) < 0)
+		return -1;
+
+	return 0;
+}
+
 /**
  * Check for the current mux state in EC. Flags representing the mux state found
  * in ec_commands.h
@@ -1632,6 +1659,25 @@
    return ret;
 }

+int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms)
+{
+	uint8_t mux_flags;
+	struct stopwatch sw;
+
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+	do {
+		google_chromeec_usb_get_pd_mux_info(port, &mux_flags);
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_WARNING, "HPD not ready after %ldms. Abort.\n", timeout_ms);
+			return -1;
+		}
+		mdelay(100);
+	} while (!(mux_flags & USB_PD_MUX_HPD_LVL) || !(mux_flags & USB_PD_MUX_DP_ENABLED));
+	printk(BIOS_INFO, "HPD ready after %lu ms\n", stopwatch_duration_msecs(&sw));
+
+	return 0;
+}
+
 int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd)
 {
    struct chromeec_command cmd = {
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 6fa58a9..a06dfa1 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -40,6 +40,14 @@
  *              >=1: Bitmask of the ports that DP device is connected
  */
 int google_chromeec_wait_for_displayport(long timeout_ms);
+/* Poll (up to `timeout_ms` ms) for a Hot-Plug Detect (HPD)
+ * event on the specified port.
+ * Return: 0 on HPD ready, -1 on timeout */
+int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms);
+/* Send command to EC to request to enter DisplayPort ALT mode on the
+ * specified port.
+ * Return: 0 on success, -1 on error */
+int google_chromeec_typec_control_enter_dp_mode(int port);

/* Device events */
 uint64_t google_chromeec_get_device_enabled_events(void);