Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57229 )
Change subject: mb/intel/kblrvp: Mark disabled SerialIO devices as `off` ......................................................................
mb/intel/kblrvp: Mark disabled SerialIO devices as `off`
Disable devicetree devices disabled in the `SerialIoDevMode` array. These devices get disabled by FSP-S, and coreboot doesn't see them.
Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 2 files changed, 4 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 2301f7e..df35e8a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -104,11 +104,10 @@
device domain 0 on device pci 04.0 off end # SA thermal subsystem + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 device pci 17.0 on end # SATA device pci 19.2 off end # I2C #4 - device pci 1e.1 on end # UART #1 - device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDCard device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 4bb00dd..8695396 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -156,15 +156,14 @@ }"
device domain 0 on + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 device pci 17.0 on end # SATA device pci 19.2 off end # I2C #4 device pci 1c.0 off end # PCI Express Port 1 device pci 1c.2 on end # PCI Express Port 3 device pci 1c.3 on end # PCI Express Port 4 device pci 1c.4 on end # PCI Express Port 5 - device pci 1e.1 on end # UART #1 - device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDXC device pci 1f.0 on
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.