Change in coreboot[master]: src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29397

Change subject: src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage
......................................................................

src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage

soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage..

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/southcluster.c
2 files changed, 21 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29397/1

diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index f485dfd..c777f72 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -43,6 +44,9 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/spi.h>
+#include <build.h>
+#include <rtc.h>
+#include <pc80/mc146818rtc.h>

void program_base_addresses(void)
 {
@@ -89,6 +93,22 @@
    write32(bcr, reg);
 }

+static void soc_rtc_init(void)
+{
+	int rtc_failed = rtc_failure();
+
+	if (rtc_failed) {
+		printk(BIOS_DEBUG,
+			"RTC Failure detected.  Resetting Date to %x/%x/%x%x\n",
+			COREBOOT_BUILD_MONTH_BCD,
+			COREBOOT_BUILD_DAY_BCD,
+			0x20,
+			COREBOOT_BUILD_YEAR_BCD);
+	}
+
+	cmos_init(rtc_failed);
+}
+
 static struct chipset_power_state power_state CAR_GLOBAL;

static void migrate_power_state(int is_recovery)
@@ -172,6 +192,7 @@
 void car_soc_post_console_init(void)
 {
    /* Continue chipset initialization */
+	soc_rtc_init();
    set_max_freq();
    spi_init();

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index ca87d63..dd0c78e 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -26,7 +26,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
@@ -149,12 +148,6 @@
    sc_add_io_resources(dev);
 }

-static void sc_rtc_init(void)
-{
-	printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);
-	cmos_init(rtc_failure());
-}
-
 static void sc_init(struct device *dev)
 {
    int i;
@@ -181,8 +174,6 @@
    /* Route SCI to IRQ9 */
    write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);

-	sc_rtc_init();
-
    if (config->disable_slp_x_stretch_sus_fail) {
    	printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
    	write32(gen_pmcon1,