Change in ...coreboot[master]: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33190
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c 14 files changed, 60 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a35e134..795e4c0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2723,13 +2723,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480 -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481 -#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 -#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 -#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 +#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI 0x3483 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI 0x3484 +#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487 +#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI 0x3486 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 86547a4..7e78bf9 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,13 +156,13 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, - PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, - PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, + PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd6a6ba..0d4e32d 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -13,19 +13,19 @@ bootblock-y += bootblock/pch.c bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c -bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-y += uart.c
+romstage-y += espi.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += lpc.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c @@ -36,6 +36,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c +ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c @@ -44,7 +45,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index f16469e..4dbd17e 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -169,7 +169,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_ESPI; const struct soc_intel_icelake_config *config = dev->chip_info;
if (!config->PmTimerDisabled) { @@ -194,7 +194,7 @@
void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_ESPI; const struct soc_intel_icelake_config *config = dev->chip_info;
/* Set unknown wake source */ diff --git a/src/soc/intel/icelake/acpi/lpc.asl b/src/soc/intel/icelake/acpi/espi.asl similarity index 96% rename from src/soc/intel/icelake/acpi/lpc.asl rename to src/soc/intel/icelake/acpi/espi.asl index f936392..4456812 100644 --- a/src/soc/intel/icelake/acpi/lpc.asl +++ b/src/soc/intel/icelake/acpi/espi.asl @@ -13,10 +13,12 @@ * GNU General Public License for more details. */
+ +/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ Device (LPCB) { Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") + Name (_DDN, "ESPI Bus Device")
Device (FWH) { diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 1b9abe6..ffd2fcc 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -32,8 +32,8 @@ /* GPIO controller */ #include "gpio.asl"
-/* LPC 0:1f.0 */ -#include "lpc.asl" +/* ESPI 0:1f.0 */ +#include "espi.asl"
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 0940791..60ab006 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -26,8 +26,8 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/espi.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index e7c010e..314a7b1 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -49,13 +49,13 @@ u16 lpcid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, - { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, - { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" }, - { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, - { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, };
static struct { @@ -170,7 +170,7 @@ static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; + pci_devfn_t dev = PCH_DEV_ESPI; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown";
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2616db1..eff1c7a 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -89,7 +89,8 @@ case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/espi.c similarity index 99% rename from src/soc/intel/icelake/lpc.c rename to src/soc/intel/icelake/espi.c index 3d05824..cca185c 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/espi.c @@ -24,9 +24,9 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <reg_script.h> +#include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h>
diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/espi.h similarity index 93% rename from src/soc/intel/icelake/include/soc/lpc.h rename to src/soc/intel/icelake/include/soc/espi.h index ebfcaa8..9308433 100644 --- a/src/soc/intel/icelake/include/soc/lpc.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -13,12 +13,10 @@ * GNU General Public License for more details. */
-#ifndef _SOC_ICELAKE_LPC_H_ -#define _SOC_ICELAKE_LPC_H_ +#ifndef _SOC_ICELAKE_ESPI_H_ +#define _SOC_ICELAKE_ESPI_H_
-#include <stdint.h> - -/* PCI Configuration Space (D31:F0): LPC */ +/* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 3cb06172..889b5c5 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -171,22 +171,24 @@ #define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) #define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)
-#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) -#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_HDA _PCH_DEV(LPC, 3) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7)
#endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1c47783..cdb39ad 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -30,10 +30,10 @@ #include <intelblocks/rtc.h> #include <intelblocks/tco.h> #include <stdlib.h> +#include <soc/espi.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 86788a5..ba06803 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -66,7 +66,7 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ESPI); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
Hello Aaron Durbin, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#2).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c 13 files changed, 59 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... File src/soc/intel/icelake/include/soc/espi.h:
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... PS4, Line 19: #include <stdint.h> Is this removal intentional? The "uint8_t get_pch_series(void)" at the end of the file seems to need it.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 5: Code-Review+2
Hello Aaron Durbin, Angel Pons, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#6).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c 13 files changed, 59 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... File src/soc/intel/icelake/include/soc/espi.h:
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... PS4, Line 19: #include <stdint.h>
Is this removal intentional? The "uint8_t get_pch_series(void)" at the end of the file seems to need […]
Thanks for pointing out this miss. Its also weird why compiler doesn't complain :(
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
Looks good to me.
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... File src/soc/intel/icelake/include/soc/espi.h:
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... PS4, Line 19: #include <stdint.h>
Thanks for pointing out this miss. […]
Oh, this is because of "indirect header inclusion".
If the files which include <espi.h> also include <stdint.h> beforehand, the compiler already knows about <stdint.h> and doesn't complain.
But this is very fragile: unrelated changes to other files can make the compiler complain about this file all of a sudden.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... File src/soc/intel/icelake/include/soc/espi.h:
https://review.coreboot.org/#/c/33190/4/src/soc/intel/icelake/include/soc/es... PS4, Line 19: #include <stdint.h>
Oh, this is because of "indirect header inclusion". […]
Agree and Thanks:)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 6:
(5 comments)
I am curious about the motivation behind the change. It doesn't look like you have gotten rid of all the lpc references anyways?
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/acpi.c File src/soc/intel/icelake/acpi.c:
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/acpi.c@172 PS6, Line 172: PCH_DEV_ESPI These should be changed to SA_DEV_ROOT? There is nothing specific to lpc/espi device here.
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/acpi.c@201 PS6, Line 201: gnvs->pm1i = -1; Same here.
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/bootblock/repo... File src/soc/intel/icelake/bootblock/report_platform.c:
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/bootblock/repo... PS6, Line 49: lpcid espi_id?
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/bootblock/repo... PS6, Line 174: lpcid espi_id
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/include/soc/pc... File src/soc/intel/icelake/include/soc/pci_devs.h:
https://review.coreboot.org/#/c/33190/6/src/soc/intel/icelake/include/soc/pc... PS6, Line 185: PCH_DEV_LPC Why was this retained?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 7:
Patch Set 6:
(5 comments)
Patch Set 6:
(5 comments)
I am curious about the motivation behind the change.
was intended to rename all soc/mb LPC reference to eSPI.
It doesn't look like you have gotten rid of all the lpc references anyways?
I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 7:
Patch Set 7:
Patch Set 6:
(5 comments)
Patch Set 6:
(5 comments)
I am curious about the motivation behind the change.
was intended to rename all soc/mb LPC reference to eSPI.
It doesn't look like you have gotten rid of all the lpc references anyways?
I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either: 1. Callback to get the right device -- LPC/ESPI 2. Have macros that define the right device and can be used by any ASL code
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 6:
(5 comments)
Patch Set 6:
(5 comments)
I am curious about the motivation behind the change.
was intended to rename all soc/mb LPC reference to eSPI.
It doesn't look like you have gotten rid of all the lpc references anyways?
I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either:
- Callback to get the right device -- LPC/ESPI
[Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ?
- Have macros that define the right device and can be used by any ASL code
[Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ?
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 6:
(5 comments)
Patch Set 6:
(5 comments)
I am curious about the motivation behind the change.
was intended to rename all soc/mb LPC reference to eSPI.
It doesn't look like you have gotten rid of all the lpc references anyways?
I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either:
- Callback to get the right device -- LPC/ESPI
[Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ?
- Have macros that define the right device and can be used by any ASL code
[Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ?
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
1. No, I was suggesting adding a callback soc_get_lpc_espi_dev() that will return appropriate device LPC or ESPI depending upon the SoC implementation. Then the SoC doesn't need to provide PCH_DEV_LPC.
2. Humm, yeah it might get tricky based on the way it is being used. I was thinking on the lines of how DPTF_CPU_DEVICE is defined. But, it might not work well here.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 7: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 6:
(5 comments)
Patch Set 6:
(5 comments)
I am curious about the motivation behind the change.
was intended to rename all soc/mb LPC reference to eSPI.
It doesn't look like you have gotten rid of all the lpc references anyways?
I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either:
- Callback to get the right device -- LPC/ESPI
[Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ?
- Have macros that define the right device and can be used by any ASL code
[Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ?
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
- No, I was suggesting adding a callback soc_get_lpc_espi_dev() that will return appropriate device LPC or ESPI depending upon the SoC implementation. Then the SoC doesn't need to provide PCH_DEV_LPC.
[Subrata] working on it.
- Humm, yeah it might get tricky based on the way it is being used. I was thinking on the lines of how DPTF_CPU_DEVICE is defined. But, it might not work well here.
[Subrata] DPTF_CPU_DEVICE is just inside device scope unlike "LPCB" used on many ASL files inside function calling hence it might be mess :(
Hello Aaron Durbin, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#8).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c M src/soc/intel/icelake/fsp_params.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/lpc.c 21 files changed, 154 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/8
Hello Aaron Durbin, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#9).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c M src/soc/intel/icelake/fsp_params.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/lpc.c 21 files changed, 156 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/9
Hello Aaron Durbin, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#10).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c M src/soc/intel/icelake/fsp_params.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/lpc.c 20 files changed, 150 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/10
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 10:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 6:
(5 comments)
> Patch Set 6: > > (5 comments) > > I am curious about the motivation behind the change. was intended to rename all soc/mb LPC reference to eSPI.
> It doesn't look like you have gotten rid of all the lpc references anyways? I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either:
- Callback to get the right device -- LPC/ESPI
[Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ?
- Have macros that define the right device and can be used by any ASL code
[Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ?
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
- No, I was suggesting adding a callback soc_get_lpc_espi_dev() that will return appropriate device LPC or ESPI depending upon the SoC implementation. Then the SoC doesn't need to provide PCH_DEV_LPC.
[Subrata] working on it.
- Humm, yeah it might get tricky based on the way it is being used. I was thinking on the lines of how DPTF_CPU_DEVICE is defined. But, it might not work well here.
[Subrata] DPTF_CPU_DEVICE is just inside device scope unlike "LPCB" used on many ASL files inside function calling hence it might be mess :(
Hi Furquan, can you please help to review
mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable soc/intel/{cml, whl}: Add option to skip HECI disable in SMM soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 10: Code-Review+1
Patch Set 10:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
> Patch Set 6: > > (5 comments) > > > Patch Set 6: > > > > (5 comments) > > > > I am curious about the motivation behind the change. > was intended to rename all soc/mb LPC reference to eSPI. > > > It doesn't look like you have gotten rid of all the lpc references anyways? > I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset
Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either:
- Callback to get the right device -- LPC/ESPI
[Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ?
- Have macros that define the right device and can be used by any ASL code
[Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ?
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
- No, I was suggesting adding a callback soc_get_lpc_espi_dev() that will return appropriate device LPC or ESPI depending upon the SoC implementation. Then the SoC doesn't need to provide PCH_DEV_LPC.
[Subrata] working on it.
- Humm, yeah it might get tricky based on the way it is being used. I was thinking on the lines of how DPTF_CPU_DEVICE is defined. But, it might not work well here.
[Subrata] DPTF_CPU_DEVICE is just inside device scope unlike "LPCB" used on many ASL files inside function calling hence it might be mess :(
Hi Furquan, can you please help to review
mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable soc/intel/{cml, whl}: Add option to skip HECI disable in SMM soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
Hi Subrata,
I looked at the latest patchset and compared it with patchset #6 and I think I like #6 more than this -- we are anyways not able to get rid of lpc references completely not even in the SoC specific code and the extra API call seems to just unnecessarily add more code which is probably not required. Since we anyways have to live with LPCB device and lpc calls, we can just use #define PCH_DEV_LPC PCH_DEV_ESPI like you had before and go ahead with that. Sorry about the back and forth.
Hello Aaron Durbin, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#11).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c 13 files changed, 59 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/11
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 11:
Patch Set 10: Code-Review+1
Patch Set 10:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
> Patch Set 7: > > > Patch Set 6: > > > > (5 comments) > > > > > Patch Set 6: > > > > > > (5 comments) > > > > > > I am curious about the motivation behind the change. > > was intended to rename all soc/mb LPC reference to eSPI. > > > > > It doesn't look like you have gotten rid of all the lpc references anyways? > > I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset > > Hi Furquan, Any comments ?
I am just wondering if it makes sense to update the common code to ensure that it uses either:
- Callback to get the right device -- LPC/ESPI
[Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ?
- Have macros that define the right device and can be used by any ASL code
[Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ?
With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
- No, I was suggesting adding a callback soc_get_lpc_espi_dev() that will return appropriate device LPC or ESPI depending upon the SoC implementation. Then the SoC doesn't need to provide PCH_DEV_LPC.
[Subrata] working on it.
- Humm, yeah it might get tricky based on the way it is being used. I was thinking on the lines of how DPTF_CPU_DEVICE is defined. But, it might not work well here.
[Subrata] DPTF_CPU_DEVICE is just inside device scope unlike "LPCB" used on many ASL files inside function calling hence it might be mess :(
Hi Furquan, can you please help to review
mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable soc/intel/{cml, whl}: Add option to skip HECI disable in SMM soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
Hi Subrata,
I looked at the latest patchset and compared it with patchset #6 and I think I like #6 more than this -- we are anyways not able to get rid of lpc references completely not even in the SoC specific code and the extra API call seems to just unnecessarily add more code which is probably not required. Since we anyways have to live with LPCB device and lpc calls, we can just use #define PCH_DEV_LPC PCH_DEV_ESPI like you had before and go ahead with that. Sorry about the back and forth.
Done
Hello Aaron Durbin, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33190
to look at the new patch set (#12).
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c M src/soc/intel/icelake/fsp_params.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/pmutil.c 15 files changed, 84 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/12
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 12:
Patch Set 11:
Patch Set 10: Code-Review+1
Patch Set 10:
Patch Set 7:
Patch Set 7:
Patch Set 7:
> Patch Set 7: > > > Patch Set 7: > > > > > Patch Set 6: > > > > > > (5 comments) > > > > > > > Patch Set 6: > > > > > > > > (5 comments) > > > > > > > > I am curious about the motivation behind the change. > > > was intended to rename all soc/mb LPC reference to eSPI. > > > > > > > It doesn't look like you have gotten rid of all the lpc references anyways? > > > I believe anything that might touches common code, i have kept as is else i guess i have rename everything now in newer patchset > > > > Hi Furquan, Any comments ? > > I am just wondering if it makes sense to update the common code to ensure that it uses either: > 1. Callback to get the right device -- LPC/ESPI [Subrata] Are you suggesting to add "_espi" in common lpc.c and other functions ? > 2. Have macros that define the right device and can be used by any ASL code [Subrata] I guess there is only one ASL where it still name as LPCB because chromeec.asl might looking at device by same name. I'm not sure if i can touch that code to look for any other name as well based on some Kconfig ? > > With this, SoC specific code can provide the right callback/macros and we don't have to carry a mix of LPC and eSPI within that code. What do you think?
- No, I was suggesting adding a callback soc_get_lpc_espi_dev() that will return appropriate device LPC or ESPI depending upon the SoC implementation. Then the SoC doesn't need to provide PCH_DEV_LPC.
[Subrata] working on it.
- Humm, yeah it might get tricky based on the way it is being used. I was thinking on the lines of how DPTF_CPU_DEVICE is defined. But, it might not work well here.
[Subrata] DPTF_CPU_DEVICE is just inside device scope unlike "LPCB" used on many ASL files inside function calling hence it might be mess :(
Hi Furquan, can you please help to review
mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable soc/intel/{cml, whl}: Add option to skip HECI disable in SMM soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
Hi Subrata,
I looked at the latest patchset and compared it with patchset #6 and I think I like #6 more than this -- we are anyways not able to get rid of lpc references completely not even in the SoC specific code and the extra API call seems to just unnecessarily add more code which is probably not required. Since we anyways have to live with LPCB device and lpc calls, we can just use #define PCH_DEV_LPC PCH_DEV_ESPI like you had before and go ahead with that. Sorry about the back and forth.
Done
I have restored patchset 7. i guess it has some pciroot_dev fix as well
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
Patch Set 12: Code-Review+2
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33190 )
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Lean Sheng Tan lean.sheng.tan@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c M src/soc/intel/icelake/fsp_params.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/pmutil.c 15 files changed, 84 insertions(+), 83 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Lean Sheng Tan: Looks good to me, but someone else must approve
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index dae5c9a..2c8fadc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2723,13 +2723,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480 -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481 -#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 -#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 -#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 +#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI 0x3483 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI 0x3484 +#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487 +#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI 0x3486 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 84471d2..54c7706 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,13 +156,13 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, - PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, - PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, + PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd6a6ba..0d4e32d 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -13,19 +13,19 @@ bootblock-y += bootblock/pch.c bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c -bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-y += uart.c
+romstage-y += espi.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += lpc.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c @@ -36,6 +36,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c +ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c @@ -44,7 +45,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index f16469e..3a46c93 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -169,7 +169,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = pcidev_on_root(0, 0); const struct soc_intel_icelake_config *config = dev->chip_info;
if (!config->PmTimerDisabled) { @@ -194,7 +194,7 @@
void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = pcidev_on_root(0, 0); const struct soc_intel_icelake_config *config = dev->chip_info;
/* Set unknown wake source */ diff --git a/src/soc/intel/icelake/acpi/lpc.asl b/src/soc/intel/icelake/acpi/espi.asl similarity index 96% rename from src/soc/intel/icelake/acpi/lpc.asl rename to src/soc/intel/icelake/acpi/espi.asl index f936392..4456812 100644 --- a/src/soc/intel/icelake/acpi/lpc.asl +++ b/src/soc/intel/icelake/acpi/espi.asl @@ -13,10 +13,12 @@ * GNU General Public License for more details. */
+ +/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ Device (LPCB) { Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") + Name (_DDN, "ESPI Bus Device")
Device (FWH) { diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 1b9abe6..ffd2fcc 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -32,8 +32,8 @@ /* GPIO controller */ #include "gpio.asl"
-/* LPC 0:1f.0 */ -#include "lpc.asl" +/* ESPI 0:1f.0 */ +#include "espi.asl"
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 0940791..aefcaa5 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -26,8 +26,8 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/espi.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -145,8 +145,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); } diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index e7c010e..a9eef40 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -46,16 +46,16 @@ };
static struct { - u16 lpcid; + u16 espiid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, - { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, - { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" }, - { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, - { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, };
static struct { @@ -170,18 +170,18 @@ static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; - uint16_t lpcid = get_dev_id(dev); + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); const char *pch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { + if (pch_table[i].espiid == espiid) { pch_type = pch_table[i].name; break; } } printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, get_dev_revision(dev), pch_type); + espiid, get_dev_revision(dev), pch_type); }
static void report_igd_info(void) diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2616db1..eff1c7a 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -89,7 +89,8 @@ case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/espi.c similarity index 90% rename from src/soc/intel/icelake/lpc.c rename to src/soc/intel/icelake/espi.c index 3d05824..9ca0c7c 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/espi.c @@ -24,9 +24,9 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <reg_script.h> +#include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h>
@@ -71,10 +71,10 @@ uint16_t lpc_did_hi_byte;
/* - * Fetch upper 8 bits on LPC device ID to determine PCH type + * Fetch upper 8 bits on ESPI device ID to determine PCH type * Adding 1 to the offset to fetch upper 8 bits */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1); + lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
if (lpc_did_hi_byte == 0x9D) return PCH_LP; @@ -87,11 +87,12 @@ #if ENV_RAMSTAGE static void soc_mirror_dmi_pcr_io_dec(void) { + struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); uint32_t io_dec_arr[] = { - pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC), + pci_read_config32(dev, ESPI_GEN1_DEC), + pci_read_config32(dev, ESPI_GEN2_DEC), + pci_read_config32(dev, ESPI_GEN3_DEC), + pci_read_config32(dev, ESPI_GEN4_DEC), }; /* Mirror these same settings in DMI PCR */ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); @@ -215,10 +216,10 @@ isa_dma_init(); pch_misc_init();
- /* Enable CLKRUN_EN for power gating LPC */ + /* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl();
- /* Set LPC Serial IRQ mode */ + /* Set ESPI Serial IRQ mode */ if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else @@ -233,13 +234,13 @@ soc_mirror_dmi_pcr_io_dec(); }
-/* Fill up LPC IO resource structure inside SoC directory */ +/* Fill up ESPI IO resource structure inside SoC directory */ void pch_lpc_soc_fill_io_resources(struct device *dev) { /* * PMC pci device gets hidden from PCI bus due to Silicon * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * LPC IO resources to ensure that ABASE falls under PCI reserved + * ESPI IO resources to ensure that ABASE falls under PCI reserved * IO memory range. * * Note: Don't add any more resource with same offset 0x20 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 127507b..ac7edd2 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -102,7 +102,7 @@ }
/* Lan */ - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 6); + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); if (!dev) params->PchLanEnable = 0; else diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/espi.h similarity index 67% rename from src/soc/intel/icelake/include/soc/lpc.h rename to src/soc/intel/icelake/include/soc/espi.h index ebfcaa8..36ee947 100644 --- a/src/soc/intel/icelake/include/soc/lpc.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -13,12 +13,12 @@ * GNU General Public License for more details. */
-#ifndef _SOC_ICELAKE_LPC_H_ -#define _SOC_ICELAKE_LPC_H_ +#ifndef _SOC_ICELAKE_ESPI_H_ +#define _SOC_ICELAKE_ESPI_H_
#include <stdint.h>
-/* PCI Configuration Space (D31:F0): LPC */ +/* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 @@ -28,19 +28,14 @@ #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 #define SERIRQ_CNTL 0x64 -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ #define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ #define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LGMR 0x98 /* LPC Generic Memory Range */ -#define BIOS_CNTL 0xdc -#define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 1) /* LE */ -#define LPC_BC_EISS (1 << 5) /* EISS */ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0)
diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 3cb06172..889b5c5 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -171,22 +171,24 @@ #define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) #define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)
-#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) -#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_HDA _PCH_DEV(LPC, 3) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7)
#endif diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h index a6ad30b..40d1360f 100644 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ b/src/soc/intel/icelake/include/soc/pcr_ids.h @@ -38,7 +38,7 @@ #define PID_SCS 0xc0 #define PID_RTC 0xc3 #define PID_ITSS 0xc4 -#define PID_LPC 0xc7 +#define PID_ESPI 0xc7 #define PID_SERIALIO 0xcb
#endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1c47783..cdb39ad 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -30,10 +30,10 @@ #include <intelblocks/rtc.h> #include <intelblocks/tco.h> #include <stdlib.h> +#include <soc/espi.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h>
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
-
Lean Sheng Tan (Code Review)
-
Subrata Banik (Code Review)
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Wonkyu Kim (Code Review)