Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29549

Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
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siemens/mc_apl3: Disable PCI clock outputs on XIO bridges

On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.

Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
1 file changed, 13 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index 3a87a4f..a271620 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -40,11 +40,6 @@
     */
    pcr_write16(PID_ITSS, 0x314c, 0x2103);

-	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
-	dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
-	if (dev)
-		pci_write_config8(dev, 0xd8, 0x3e);
-
    /* Enable CLKRUN_EN for power gating LPC */
    lpc_enable_pci_clk_cntl();

@@ -62,8 +57,21 @@
    	cmd = pci_read_config16(dev, PCI_COMMAND);
    	cmd |= PCI_COMMAND_MASTER;
    	pci_write_config16(dev, PCI_COMMAND, cmd);
+
+		/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream
+		 * XIO2001 PCIe to PCI Bridge.
+		 */
+		if (dev->bus->dev)
+			pci_write_config8(dev->bus->dev, 0xd8, 0x1d);
    }

+	/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
+	 * Bridge on this mainboard.
+	 */
+	dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0);
+	if (dev->bus->dev)
+		pci_write_config8(dev->bus->dev, 0xd8, 0x3c);
+
    /* Set Full Reset Bit in Reset Control Register (I/O port CF9h).
     * When Bit 3 is set to 1 and then the reset button is pressed the PCH
     * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard