You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32120
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly. ......................................................................
google/kukui: Configure AP_IN_SLEEP_L correctly.
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM can control it.
BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu youcheng@google.com --- M src/mainboard/google/kukui/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32120/1
diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..1193bb3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -32,8 +32,7 @@
setup_chromeos_gpios();
- /* Declare we are in S0 */ - gpio_output(AP_IN_SLEEP_L, 1); + gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0);
mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32120 )
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly. ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/32120/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32120/1//COMMIT_MSG@7 PS1, Line 7: google/kukui: Configure AP_IN_SLEEP_L correctly. Please remove the dot/period at the end of the git commit message summary.
https://review.coreboot.org/#/c/32120/1//COMMIT_MSG@10 PS1, Line 10: SPM What is SPM?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32120 )
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly. ......................................................................
Patch Set 1: Code-Review+1
This should be the right config. Please update commit message according to Paul's feedback.
Hello Julius Werner, Paul Menzel, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32120
to look at the new patch set (#2).
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly ......................................................................
google/kukui: Configure AP_IN_SLEEP_L correctly
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM (a power management component of MT8183) can control it.
BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu youcheng@google.com --- M src/mainboard/google/kukui/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32120/2
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32120 )
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32120/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32120/1//COMMIT_MSG@7 PS1, Line 7: google/kukui: Configure AP_IN_SLEEP_L correctly.
Please remove the dot/period at the end of the git commit message summary.
Done
https://review.coreboot.org/#/c/32120/1//COMMIT_MSG@10 PS1, Line 10: SPM
What is SPM?
It's MTK's power management component. Description added.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32120 )
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32120 )
Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly ......................................................................
google/kukui: Configure AP_IN_SLEEP_L correctly
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM (a power management component of MT8183) can control it.
BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu youcheng@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120 Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/kukui/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Hung-Te Lin: Looks good to me, approved
diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..1193bb3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -32,8 +32,7 @@
setup_chromeos_gpios();
- /* Declare we are in S0 */ - gpio_output(AP_IN_SLEEP_L, 1); + gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0);
mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
-
Hung-Te Lin (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
You-Cheng Syu (Code Review)