Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30734
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
AGESA fam15tn boards: Clean up devicetree
Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2.
Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/parmer/devicetree.cb M src/mainboard/amd/thatcher/devicetree.cb M src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb M src/mainboard/lenovo/g505s/devicetree.cb M src/mainboard/msi/ms7721/devicetree.cb 5 files changed, 308 insertions(+), 313 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30734/1
diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index da0028c..e619def 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -22,50 +22,49 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
- chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -78,7 +77,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index cee1608..4ae1ba9 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -22,65 +22,64 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x8 + device pci 3.0 off end + device pci 4.0 on end # LAN + device pci 5.0 on end # PCIE MINI0 + device pci 6.0 on end # PCIE MINI1 + device pci 7.0 off end + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x8 - device pci 3.0 off end - device pci 4.0 on end # LAN - device pci 5.0 on end # PCIE MINI0 - device pci 6.0 on end # PCIE MINI1 - device pci 7.0 off end - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/lpc47n217 + device pnp 2e.3 off # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/lpc47n217 - device pnp 2e.3 off # Parallel - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end #chip superio/smsc/lpc47n217 - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end #chip superio/smsc/lpc47n217 + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
+ chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -93,7 +92,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index 75d45d3..ad59974 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -22,51 +22,50 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address end - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address + end + end + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
+ chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -79,7 +78,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 0b8f267..99f42d6 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -22,55 +22,54 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 off end + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 off end # + device pci 7.0 off end # + device pci 8.0 off end # NB/SB Link P2P bridge ? + device pci 9.0 off end # + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 off end # - device pci 7.0 off end # - device pci 8.0 off end # NB/SB Link P2P bridge ? - device pci 9.0 off end # - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # FCH USB XHCI Controller HC0 - device pci 11.0 on end # FCH SATA Controller [AHCI mode] - device pci 12.0 on end # FCH USB OHCI Controller - device pci 12.2 on end # FCH USB EHCI Controller - device pci 13.0 on end # FCH USB OHCI Controller - device pci 13.2 on end # FCH USB EHCI Controller - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # FCH Azalia Controller - device pci 14.3 on # FCH LPC Bridge [1022:780e] - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # FCH USB XHCI Controller HC0 + device pci 11.0 on end # FCH SATA Controller [AHCI mode] + device pci 12.0 on end # FCH USB OHCI Controller + device pci 12.2 on end # FCH USB EHCI Controller + device pci 13.0 on end # FCH USB OHCI Controller + device pci 13.2 on end # FCH USB EHCI Controller + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address end - device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # FCH Azalia Controller + device pci 14.3 on # FCH LPC Bridge [1022:780e] + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address + end + end + device pci 14.4 on end # FCH PCI Bridge [1022:780f] + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
+ chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -83,7 +82,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index 3507925..d3991f1 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -23,142 +23,141 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x990e + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe x16 + device pci 3.0 off end # - + device pci 4.0 on end # PCIE Realtek LAN + device pci 5.0 on end # PCIE x1 (1) + device pci 6.0 on end # PCIE x1 (2) + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x990e - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe x16 - device pci 3.0 off end # - - device pci 4.0 on end # PCIE Realtek LAN - device pci 5.0 on end # PCIE x1 (1) - device pci 6.0 on end # PCIE x1 (2) - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB OHCI + device pci 12.2 on end # USB EHCI + device pci 13.0 on end # USB OHCI + device pci 13.2 on end # USB EHCI + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # Azalia (Audio) + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x0f" + register "multi_function_register_3" = "0x2f" + register "multi_function_register_4" = "0x04" + register "multi_function_register_5" = "0x3e"
- chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB OHCI - device pci 12.2 on end # USB EHCI - device pci 13.0 on end # USB OHCI - device pci 13.2 on end # USB EHCI - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + # HWM configuration registers + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_temp_sensor_type" = "0x08" + + device pnp 4e.00 off end + device pnp 4e.01 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # Azalia (Audio) - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad - register "multi_function_register_1" = "0x01" - register "multi_function_register_2" = "0x0f" - register "multi_function_register_3" = "0x2f" - register "multi_function_register_4" = "0x04" - register "multi_function_register_5" = "0x3e" + device pnp 4e.03 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + irq 0xf0 = 0x44 # PRT Mode Select Register + end + device pnp 4e.04 on # Hardware Monitor + io 0x60 = 0x225 # Fintek datasheet says 0x295. + irq 0x70 = 0 + end + device pnp 4e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 4e.06 on # GPIO + # ! GPIO config is disabled because the code in romstage.c + # ! has already taken care of it + #io 0x60 = 0xa00 + #irq 0xe0 = 0x04 # GPIO1 output + #irq 0xe1 = 0xff # GPIO1 output data + #irq 0xe3 = 0x04 # GPIO1 drive enable + #irq 0xe4 = 0x00 # GPIO1 PME enable + #irq 0xe5 = 0x00 # GPIO1 input detect select + #irq 0xe6 = 0x40 # GPIO1 event status
- # HWM configuration registers - register "hwm_smbus_address" = "0x98" - register "hwm_smbus_control_reg" = "0x02" - register "hwm_fan_type_sel_reg" = "0x00" - register "hwm_fan1_temp_adj_rate_reg" = "0x33" - register "hwm_fan_mode_sel_reg" = "0x07" - register "hwm_fan1_idx_rpm_mode" = "0x0e" - register "hwm_fan1_seg1_speed_count" = "0xff" - register "hwm_fan1_seg2_speed_count" = "0x0e" - register "hwm_fan1_seg3_speed_count" = "0x07" - register "hwm_fan1_temp_map_sel" = "0x8c" - register "hwm_temp_sensor_type" = "0x08" + #irq 0xd0 = 0x00 # GPIO2 output + #irq 0xd1 = 0xff # GPIO2 output data + #irq 0xd3 = 0x00 # GPIO2 drive enable
- device pnp 4e.00 off end - device pnp 4e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.03 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 3 - irq 0xf0 = 0x44 # PRT Mode Select Register - end - device pnp 4e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 4e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 4e.06 on # GPIO - # ! GPIO config is disabled because the code in romstage.c - # ! has already taken care of it - #io 0x60 = 0xa00 - #irq 0xe0 = 0x04 # GPIO1 output - #irq 0xe1 = 0xff # GPIO1 output data - #irq 0xe3 = 0x04 # GPIO1 drive enable - #irq 0xe4 = 0x00 # GPIO1 PME enable - #irq 0xe5 = 0x00 # GPIO1 input detect select - #irq 0xe6 = 0x40 # GPIO1 event status + #irq 0xc0 = 0x00 # GPIO3 output + #irq 0xc1 = 0xff # GPIO3 output data
- #irq 0xd0 = 0x00 # GPIO2 output - #irq 0xd1 = 0xff # GPIO2 output data - #irq 0xd3 = 0x00 # GPIO2 drive enable + #irq 0xb0 = 0x04 # GPIO4 output + #irq 0xb1 = 0x04 # GPIO4 output data + #irq 0xb3 = 0x04 # GPIO4 drive enable + #irq 0xb4 = 0x00 # GPIO4 PME enable + #irq 0xb5 = 0x00 # GPIO4 input detect select + #irq 0xb6 = 0x00 # GPIO4 event status
- #irq 0xc0 = 0x00 # GPIO3 output - #irq 0xc1 = 0xff # GPIO3 output data + #irq 0xa0 = 0x00 # GPIO5 output + #irq 0xa1 = 0x1f # GPIO5 output data + #irq 0xa3 = 0x00 # GPIO5 drive enable + #irq 0xa4 = 0x00 # GPIO5 PME enable + #irq 0xa5 = 0xff # GPIO5 input detect select + #irq 0xa6 = 0xe0 # GPIO5 event status
- #irq 0xb0 = 0x04 # GPIO4 output - #irq 0xb1 = 0x04 # GPIO4 output data - #irq 0xb3 = 0x04 # GPIO4 drive enable - #irq 0xb4 = 0x00 # GPIO4 PME enable - #irq 0xb5 = 0x00 # GPIO4 input detect select - #irq 0xb6 = 0x00 # GPIO4 event status + #irq 0x90 = 0x00 # GPIO6 output + #irq 0x91 = 0xff # GPIO6 output data + #irq 0x93 = 0x00 # GPIO6 drive enable
- #irq 0xa0 = 0x00 # GPIO5 output - #irq 0xa1 = 0x1f # GPIO5 output data - #irq 0xa3 = 0x00 # GPIO5 drive enable - #irq 0xa4 = 0x00 # GPIO5 PME enable - #irq 0xa5 = 0xff # GPIO5 input detect select - #irq 0xa6 = 0xe0 # GPIO5 event status + #irq 0x80 = 0x00 # GPIO7 output + #irq 0x81 = 0xff # GPIO7 output data + #irq 0x83 = 0x00 # GPIO7 drive enable + end
- #irq 0x90 = 0x00 # GPIO6 output - #irq 0x91 = 0xff # GPIO6 output data - #irq 0x93 = 0x00 # GPIO6 drive enable + device pnp 4e.07 on end # WDT + device pnp 4e.08 off end # CIR + device pnp 4e.0a on end # PME + end # f71869ad + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 (PCI slot on board) + device pci 14.5 on end # USB OHCI + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # unused + device pci 15.1 off end # unused + device pci 15.2 off end # unused + device pci 15.3 off end # unused
- #irq 0x80 = 0x00 # GPIO7 output - #irq 0x81 = 0xff # GPIO7 output data - #irq 0x83 = 0x00 # GPIO7 drive enable - end + end #chip southbridge/amd/agesa/hudson
- device pnp 4e.07 on end # WDT - device pnp 4e.08 off end # CIR - device pnp 4e.0a on end # PME - end # f71869ad - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 (PCI slot on board) - device pci 14.5 on end # USB OHCI - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # unused - device pci 15.1 off end # unused - device pci 15.2 off end # unused - device pci 15.3 off end # unused - - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -171,7 +170,7 @@ { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
Patch Set 3: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
Patch Set 3: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
Patch Set 3: Code-Review+1
mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
Patch Set 3: Code-Review+1
Finally I tested this change on my Lenovo G505S laptop and it still boots :) Compared to this board status report from the end of December - https://review.coreboot.org/cgit/board-status.git/tree/lenovo/g505s/4.9-8-g4... - there are no real changes at Linux kernel dmesg log, but now lspci -vvxxx shows a different PCI config space for 00:18.2 device, hopefully as expected and these differences below are okay (meld/kdiff3 to highlight)
Please let me know if any further tests are needed ( are there any software tests for 00:18.2 device which I could run to verify its' functionality? )
P.S. Also, I've been CC'd regarding CB:21624 change but it's marked as [WIP]. Is it ready for testing on real hardware?
===> BEFORE :
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) Processor Function 2 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 21 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: c0 ff f8 01 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 02 00 98 00 28 18 80: 0a 00 00 00 05 00 80 00 00 00 00 3c 00 00 02 00 90: 00 00 01 03 92 88 59 9f 2f 81 0f 8d a1 00 00 00 a0: 20 02 1d 03 00 00 00 00 00 00 32 80 00 00 00 00 b0: 68 2c 7a 7b 3e 00 00 00 4f df f9 e2 6e ad 02 6c c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: e0 79 ff ff af a6 ab ff ff eb ff bb f7 ce 95 ef e0: e0 c2 86 ee b7 ea ef 77 e7 43 f7 7b f5 f0 61 ab f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ===> AFTER: 00:18.2 ---//--- 00: 22 10 02 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 21 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: c0 ff f8 01 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 02 00 98 00 28 18 80: 0a 00 00 00 05 00 80 00 00 00 00 3c 00 00 02 00 90: 00 00 01 03 92 88 59 9f 2f 81 0f 8d a1 00 00 00 a0: a0 02 1d 03 00 00 00 00 00 00 32 80 00 00 00 00 b0: 5e b3 29 db ef 00 00 00 4f df f9 a2 6e 84 02 6c c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: e0 79 fd ff 2f a6 ab bf ec 98 71 ce f7 86 97 ef e0: f0 c2 84 ee be ea ed 7f e7 43 f7 7b b5 f0 61 ab f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
Patch Set 3:
Patch Set 3: Code-Review+1
Finally I tested this change on my Lenovo G505S laptop and it still boots :) Compared to this board status report from the end of December - https://review.coreboot.org/cgit/board-status.git/tree/lenovo/g505s/4.9-8-g4... - there are no real changes at Linux kernel dmesg log, but now lspci -vvxxx shows a different PCI config space for 00:18.2 device, hopefully as expected and these differences below are okay (meld/kdiff3 to highlight)
I did not check closer yet, but some of those 0:18.2 registers are timestamps and trace records. I think they change for every boot and deal with DDR3 training.
Not something that this change would have anything to do with, even though commit mentions 0:18.2.
Please let me know if any further tests are needed ( are there any software tests for 00:18.2 device which I could run to verify its' functionality? )
It's really a no-op change wrt 0:18.2.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30734 )
Change subject: AGESA fam15tn boards: Clean up devicetree ......................................................................
AGESA fam15tn boards: Clean up devicetree
Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2.
Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/30734 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: mikeb mikeb mikebdp2@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/parmer/devicetree.cb M src/mainboard/amd/thatcher/devicetree.cb M src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb M src/mainboard/lenovo/g505s/devicetree.cb M src/mainboard/msi/ms7721/devicetree.cb 5 files changed, 308 insertions(+), 313 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve mikeb mikeb: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index da0028c..e619def 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -22,50 +22,49 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
- chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -78,7 +77,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index cee1608..4ae1ba9 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -22,65 +22,64 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x8 + device pci 3.0 off end + device pci 4.0 on end # LAN + device pci 5.0 on end # PCIE MINI0 + device pci 6.0 on end # PCIE MINI1 + device pci 7.0 off end + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x8 - device pci 3.0 off end - device pci 4.0 on end # LAN - device pci 5.0 on end # PCIE MINI0 - device pci 6.0 on end # PCIE MINI1 - device pci 7.0 off end - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/lpc47n217 + device pnp 2e.3 off # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/lpc47n217 - device pnp 2e.3 off # Parallel - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end #chip superio/smsc/lpc47n217 - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end #chip superio/smsc/lpc47n217 + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
+ chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -93,7 +92,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index 75d45d3..ad59974 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -22,51 +22,50 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address end - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address + end + end + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
+ chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -79,7 +78,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 0b8f267..99f42d6 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -22,55 +22,54 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 off end + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 off end # + device pci 7.0 off end # + device pci 8.0 off end # NB/SB Link P2P bridge ? + device pci 9.0 off end # + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 off end # - device pci 7.0 off end # - device pci 8.0 off end # NB/SB Link P2P bridge ? - device pci 9.0 off end # - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # FCH USB XHCI Controller HC0 - device pci 11.0 on end # FCH SATA Controller [AHCI mode] - device pci 12.0 on end # FCH USB OHCI Controller - device pci 12.2 on end # FCH USB EHCI Controller - device pci 13.0 on end # FCH USB OHCI Controller - device pci 13.2 on end # FCH USB EHCI Controller - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # FCH Azalia Controller - device pci 14.3 on # FCH LPC Bridge [1022:780e] - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # FCH USB XHCI Controller HC0 + device pci 11.0 on end # FCH SATA Controller [AHCI mode] + device pci 12.0 on end # FCH USB OHCI Controller + device pci 12.2 on end # FCH USB EHCI Controller + device pci 13.0 on end # FCH USB OHCI Controller + device pci 13.2 on end # FCH USB EHCI Controller + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address end - device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # FCH Azalia Controller + device pci 14.3 on # FCH LPC Bridge [1022:780e] + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address + end + end + device pci 14.4 on end # FCH PCI Bridge [1022:780f] + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson
+ chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -83,7 +82,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index 3507925..d3991f1 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -23,142 +23,141 @@
device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x990e + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe x16 + device pci 3.0 off end # - + device pci 4.0 on end # PCIE Realtek LAN + device pci 5.0 on end # PCIE x1 (1) + device pci 6.0 on end # PCIE x1 (2) + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x990e - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe x16 - device pci 3.0 off end # - - device pci 4.0 on end # PCIE Realtek LAN - device pci 5.0 on end # PCIE x1 (1) - device pci 6.0 on end # PCIE x1 (2) - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB OHCI + device pci 12.2 on end # USB EHCI + device pci 13.0 on end # USB OHCI + device pci 13.2 on end # USB EHCI + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # Azalia (Audio) + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x0f" + register "multi_function_register_3" = "0x2f" + register "multi_function_register_4" = "0x04" + register "multi_function_register_5" = "0x3e"
- chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB OHCI - device pci 12.2 on end # USB EHCI - device pci 13.0 on end # USB OHCI - device pci 13.2 on end # USB EHCI - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + # HWM configuration registers + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_temp_sensor_type" = "0x08" + + device pnp 4e.00 off end + device pnp 4e.01 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # Azalia (Audio) - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad - register "multi_function_register_1" = "0x01" - register "multi_function_register_2" = "0x0f" - register "multi_function_register_3" = "0x2f" - register "multi_function_register_4" = "0x04" - register "multi_function_register_5" = "0x3e" + device pnp 4e.03 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + irq 0xf0 = 0x44 # PRT Mode Select Register + end + device pnp 4e.04 on # Hardware Monitor + io 0x60 = 0x225 # Fintek datasheet says 0x295. + irq 0x70 = 0 + end + device pnp 4e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 4e.06 on # GPIO + # ! GPIO config is disabled because the code in romstage.c + # ! has already taken care of it + #io 0x60 = 0xa00 + #irq 0xe0 = 0x04 # GPIO1 output + #irq 0xe1 = 0xff # GPIO1 output data + #irq 0xe3 = 0x04 # GPIO1 drive enable + #irq 0xe4 = 0x00 # GPIO1 PME enable + #irq 0xe5 = 0x00 # GPIO1 input detect select + #irq 0xe6 = 0x40 # GPIO1 event status
- # HWM configuration registers - register "hwm_smbus_address" = "0x98" - register "hwm_smbus_control_reg" = "0x02" - register "hwm_fan_type_sel_reg" = "0x00" - register "hwm_fan1_temp_adj_rate_reg" = "0x33" - register "hwm_fan_mode_sel_reg" = "0x07" - register "hwm_fan1_idx_rpm_mode" = "0x0e" - register "hwm_fan1_seg1_speed_count" = "0xff" - register "hwm_fan1_seg2_speed_count" = "0x0e" - register "hwm_fan1_seg3_speed_count" = "0x07" - register "hwm_fan1_temp_map_sel" = "0x8c" - register "hwm_temp_sensor_type" = "0x08" + #irq 0xd0 = 0x00 # GPIO2 output + #irq 0xd1 = 0xff # GPIO2 output data + #irq 0xd3 = 0x00 # GPIO2 drive enable
- device pnp 4e.00 off end - device pnp 4e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.03 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 3 - irq 0xf0 = 0x44 # PRT Mode Select Register - end - device pnp 4e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 4e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 4e.06 on # GPIO - # ! GPIO config is disabled because the code in romstage.c - # ! has already taken care of it - #io 0x60 = 0xa00 - #irq 0xe0 = 0x04 # GPIO1 output - #irq 0xe1 = 0xff # GPIO1 output data - #irq 0xe3 = 0x04 # GPIO1 drive enable - #irq 0xe4 = 0x00 # GPIO1 PME enable - #irq 0xe5 = 0x00 # GPIO1 input detect select - #irq 0xe6 = 0x40 # GPIO1 event status + #irq 0xc0 = 0x00 # GPIO3 output + #irq 0xc1 = 0xff # GPIO3 output data
- #irq 0xd0 = 0x00 # GPIO2 output - #irq 0xd1 = 0xff # GPIO2 output data - #irq 0xd3 = 0x00 # GPIO2 drive enable + #irq 0xb0 = 0x04 # GPIO4 output + #irq 0xb1 = 0x04 # GPIO4 output data + #irq 0xb3 = 0x04 # GPIO4 drive enable + #irq 0xb4 = 0x00 # GPIO4 PME enable + #irq 0xb5 = 0x00 # GPIO4 input detect select + #irq 0xb6 = 0x00 # GPIO4 event status
- #irq 0xc0 = 0x00 # GPIO3 output - #irq 0xc1 = 0xff # GPIO3 output data + #irq 0xa0 = 0x00 # GPIO5 output + #irq 0xa1 = 0x1f # GPIO5 output data + #irq 0xa3 = 0x00 # GPIO5 drive enable + #irq 0xa4 = 0x00 # GPIO5 PME enable + #irq 0xa5 = 0xff # GPIO5 input detect select + #irq 0xa6 = 0xe0 # GPIO5 event status
- #irq 0xb0 = 0x04 # GPIO4 output - #irq 0xb1 = 0x04 # GPIO4 output data - #irq 0xb3 = 0x04 # GPIO4 drive enable - #irq 0xb4 = 0x00 # GPIO4 PME enable - #irq 0xb5 = 0x00 # GPIO4 input detect select - #irq 0xb6 = 0x00 # GPIO4 event status + #irq 0x90 = 0x00 # GPIO6 output + #irq 0x91 = 0xff # GPIO6 output data + #irq 0x93 = 0x00 # GPIO6 drive enable
- #irq 0xa0 = 0x00 # GPIO5 output - #irq 0xa1 = 0x1f # GPIO5 output data - #irq 0xa3 = 0x00 # GPIO5 drive enable - #irq 0xa4 = 0x00 # GPIO5 PME enable - #irq 0xa5 = 0xff # GPIO5 input detect select - #irq 0xa6 = 0xe0 # GPIO5 event status + #irq 0x80 = 0x00 # GPIO7 output + #irq 0x81 = 0xff # GPIO7 output data + #irq 0x83 = 0x00 # GPIO7 drive enable + end
- #irq 0x90 = 0x00 # GPIO6 output - #irq 0x91 = 0xff # GPIO6 output data - #irq 0x93 = 0x00 # GPIO6 drive enable + device pnp 4e.07 on end # WDT + device pnp 4e.08 off end # CIR + device pnp 4e.0a on end # PME + end # f71869ad + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 (PCI slot on board) + device pci 14.5 on end # USB OHCI + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # unused + device pci 15.1 off end # unused + device pci 15.2 off end # unused + device pci 15.3 off end # unused
- #irq 0x80 = 0x00 # GPIO7 output - #irq 0x81 = 0xff # GPIO7 output data - #irq 0x83 = 0x00 # GPIO7 drive enable - end + end #chip southbridge/amd/agesa/hudson
- device pnp 4e.07 on end # WDT - device pnp 4e.08 off end # CIR - device pnp 4e.0a on end # PME - end # f71869ad - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 (PCI slot on board) - device pci 14.5 on end # USB OHCI - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # unused - device pci 15.1 off end # unused - device pci 15.2 off end # unused - device pci 15.3 off end # unused - - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -171,7 +170,7 @@ { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex
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