[S] Change in coreboot[master]: mb/google/dedede/var/boxy:Add power limits for Boxy

[Stanley Wu (Code Review)]

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76876?usp=email )

Change subject: mb/google/dedede/var/boxy:Add power limits for Boxy
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mb/google/dedede/var/boxy:Add power limits for Boxy

Add PLx from JSL PDG in boxy devicetree.

BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy

Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu 
---
M src/mainboard/google/dedede/variants/boxy/overridetree.cb
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/76876/1

diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
index ecf71ae..10ae686 100644
--- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
@@ -33,6 +33,19 @@
    	},
    }"

+	# Power limit config
+	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
+	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+		.tdp_pl4 = 60,
+	}"
+
    # Enable Root Port 3 (index 2) for LAN
    # External PCIe port 7 is mapped to PCIe Root Port 3
    register "PcieRpEnable[2]" = "1"