Change in coreboot[master]: mb/google/volteer/var/terrador: update gpio setting and overridetree.cb
David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: update gpio setting and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: update gpio setting and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador.
BUG=b:b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 227 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/1
diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index a54aeca..198d7e1 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -1,15 +1,156 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <baseboard/gpio.h> +#include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h>
/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> ESPI_RST_L */ + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A23 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_A23, NONE),
+ /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B5 : ISH_I2C0_CVF_SDA ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D17 : ISH_GP4 ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E2 : SPI1_IO3 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E8 : SPI1_CS1# ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E17, NONE, DEEP, EDGE_SINGLE), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F8 : I2S_MCLK2_INOUT ==> NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : Reserved ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H11, NONE), + /* H12 : M2_SKT2_CFG0 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + /* R6 : I2S1_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), };
-const struct pad_config *variant_base_gpio_table(size_t *num) +const struct pad_config *variant_override_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -17,7 +158,38 @@
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), };
const struct pad_config *variant_early_gpio_table(size_t *num) @@ -25,12 +197,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h index 0075826..fe512d8 100644 --- a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h @@ -5,6 +5,8 @@
#include <baseboard/gpio.h>
-/* Copied from baseboard and may need to change for the new variant. */ +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17
#endif diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 75422d8..24842a1 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -1,4 +1,54 @@ chip soc/intel/tigerlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end # I2C #0 0xA0E8 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HD audio 0xA0C8-A0CF end end
David Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador.
BUG=b:b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 227 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#3).
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 227 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#4).
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 256 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/4
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42302/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/terrador/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/42302/4/src/mainboard/google/voltee... PS4, Line 28: probe the max98373 and alc5682i are on the MLB, right? in that case, there's no need for "probe" - the devices are always present. you won't need to use the audio DB field in fw_config.
https://review.coreboot.org/c/coreboot/+/42302/4/src/mainboard/google/voltee... PS4, Line 53: chip drivers/generic/max98357a : register "hid" = ""MX98357A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" : register "sdmode_delay" = "5" : device generic 0 on : probe AUDIO MAX98357_ALC5682I_I2S : end : end : chip drivers/intel/soundwire : device generic 0 on : probe AUDIO MAX98373_ALC5682_SNDW : chip drivers/soundwire/alc5682 : # SoundWire Link 0 ID 1 : register "desc" = ""Headset Codec"" : device generic 0.1 on end : end : chip drivers/soundwire/max98373 : # SoundWire Link 1 ID 3 : register "desc" = ""Left Speaker Amp"" : device generic 1.3 on end : end : chip drivers/soundwire/max98373 : # SoundWire Link 1 ID 7 : register "desc" = ""Right Speaker Amp"" : device generic 1.7 on end : end : end : end i didn't see any of these devices on your schematics. remove? leave 1f.3 enabled.
Hello build bot (Jenkins), Kane Chen, Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#5).
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 222 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/5
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
Patch Set 5:
(2 comments)
Thanks.
https://review.coreboot.org/c/coreboot/+/42302/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/terrador/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/42302/4/src/mainboard/google/voltee... PS4, Line 28: probe
the max98373 and alc5682i are on the MLB, right? […]
Yes, the max98373 and alc5682i are on the MLB. Thanks.
https://review.coreboot.org/c/coreboot/+/42302/4/src/mainboard/google/voltee... PS4, Line 53: chip drivers/generic/max98357a : register "hid" = ""MX98357A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" : register "sdmode_delay" = "5" : device generic 0 on : probe AUDIO MAX98357_ALC5682I_I2S : end : end : chip drivers/intel/soundwire : device generic 0 on : probe AUDIO MAX98373_ALC5682_SNDW : chip drivers/soundwire/alc5682 : # SoundWire Link 0 ID 1 : register "desc" = ""Headset Codec"" : device generic 0.1 on end : end : chip drivers/soundwire/max98373 : # SoundWire Link 1 ID 3 : register "desc" = ""Left Speaker Amp"" : device generic 1.3 on end : end : chip drivers/soundwire/max98373 : # SoundWire Link 1 ID 7 : register "desc" = ""Right Speaker Amp"" : device generic 1.7 on end : end : end : end
i didn't see any of these devices on your schematics. remove? […]
Removed.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio setting and overridetree.cb ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42302/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42302/5//COMMIT_MSG@7 PS5, Line 7: setting settings
https://review.coreboot.org/c/coreboot/+/42302/5//COMMIT_MSG@10 PS5, Line 10: generate gpio setting and overridetree.cb for terrador. Please re-flow for 75 character line length limit.
Hello build bot (Jenkins), Kane Chen, Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#6).
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 222 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/6
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42302/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42302/5//COMMIT_MSG@7 PS5, Line 7: setting
settings
Done
https://review.coreboot.org/c/coreboot/+/42302/5//COMMIT_MSG@10 PS5, Line 10: generate gpio setting and overridetree.cb for terrador.
Please re-flow for 75 character line length limit.
Done
Hello build bot (Jenkins), Kane Chen, Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#7).
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 223 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/7
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/7/src/mainboard/google/voltee... PS7, Line 9: static const struct pad_config gpio_table[] = { a bunch of these GPIOs are identical to the baseboard. you should be able to remove a bunch of duplicates.
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 10:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... PS10, Line 134: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */
'PRES' may be misspelled - perhaps 'PRESS'?
This is signal name from schematic.
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/7/src/mainboard/google/voltee... PS7, Line 9: static const struct pad_config gpio_table[] = {
a bunch of these GPIOs are identical to the baseboard. […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... PS10, Line 134: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */
This is signal name from schematic.
build bot tries to be helpful 😄
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... PS10, Line 100: /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPI(GPP_E12, NONE, DEEP), : Because you are overriding one of the GPIOs in the baseboard's early_gpio_table[] array, you need to define a seperate early_gpio_table[] for terrodor in this file.
To do so, you can copy the early_gpio_table structure from mainboard/google/volteer/variant/baseboard/gpio.c and paste it into this file, and then change the GPP_E12 entry in that early_gpio_table that you just copied to this file to match what you've defined here for GPP_E12.
You will also need to add the following routine to this file :
const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; }
Hello build bot (Jenkins), Kane Chen, Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#11).
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 237 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/11
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/11/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/11/src/mainboard/google/volte... PS11, Line 134: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ 'PRES' may be misspelled - perhaps 'PRESS'?
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/10/src/mainboard/google/volte... PS10, Line 100: /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPI(GPP_E12, NONE, DEEP), :
Because you are overriding one of the GPIOs in the baseboard's early_gpio_table[] array, you need to […]
Done. Copy the GPP_E12 entry in that early_gpio_table. Thanks.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/11/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/11/src/mainboard/google/volte... PS11, Line 175: /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ : PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), : : /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ : PAD_CFG_GPI(GPP_A17, NONE, DEEP), : : /* B11 : PMCALERT# ==> PCH_WP_OD */ : PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), : : /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ : PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), : : /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ : PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), : : /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ : PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), : : /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ : PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), : : /* C0 : SMBCLK ==> EN_PP3300_WLAN */ : PAD_CFG_GPO(GPP_C0, 1, DEEP), : : /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ : PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), : : /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), : : /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPI(GPP_E12, NONE, DEEP), : }; could you group these similarly to the above table? (all GPP_A next to each other, GPP_B, etc.)
Hello build bot (Jenkins), Kane Chen, Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#12).
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 254 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/12
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/11/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/11/src/mainboard/google/volte... PS11, Line 175: /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ : PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), : : /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ : PAD_CFG_GPI(GPP_A17, NONE, DEEP), : : /* B11 : PMCALERT# ==> PCH_WP_OD */ : PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), : : /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ : PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), : : /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ : PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), : : /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ : PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), : : /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ : PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), : : /* C0 : SMBCLK ==> EN_PP3300_WLAN */ : PAD_CFG_GPO(GPP_C0, 1, DEEP), : : /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ : PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), : : /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), : : /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPI(GPP_E12, NONE, DEEP), : };
could you group these similarly to the above table? (all GPP_A next to each other, GPP_B, etc. […]
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 158: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ 'PRES' may be misspelled - perhaps 'PRESS'?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 12:
(5 comments)
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 8: /* Leave eSPI pins untouched from default settings */ Please remove this comment. I noticed that variant/volteer/gpio.c also had this comment, so I have submitted a change to remove this comment from there as well. Thank you.
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 9: gpio_table Please name this "override_gpio_table" to make it more clear that this is an override table and not the base table.
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 193: gpio_table Please change to "override_gpio_table".
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 194: gpio_table Please change to "override_gpio_table".
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 17: device pci 15.0 on : chip drivers/i2c/generic : register "hid" = ""10EC5682"" : register "name" = ""RT58"" : register "desc" = ""Headset Codec"" : register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" : # Set the jd_src to RT5668_JD1 for jack detection : register "property_count" = "1" : register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" : register "property_list[0].name" = ""realtek,jd-src"" : register "property_list[0].integer" = "1" : device i2c 1a on : end : end : chip drivers/i2c/max98373 : register "vmon_slot_no" = "0" : register "imon_slot_no" = "1" : register "uid" = "0" : register "desc" = ""Right Speaker Amp"" : register "name" = ""MAXR"" : device i2c 31 on : end : end : chip drivers/i2c/max98373 : register "vmon_slot_no" = "2" : register "imon_slot_no" = "3" : register "uid" = "1" : register "desc" = ""Left Speaker Amp"" : register "name" = ""MAXL"" : device i2c 32 on : end : end : end # I2C #0 0xA0E8 : Please rebase your change (https://review.coreboot.org/c/coreboot/+/42302) on top of this change (https://review.coreboot.org/c/coreboot/+/42550/) as it has already been +2'd and will merge before this CL, and it modifies terrador's overridetree.cb to add a couple of items.
Hello build bot (Jenkins), Kane Chen, Derek Huang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42302
to look at the new patch set (#13).
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 256 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/13
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 13: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 8: /* Leave eSPI pins untouched from default settings */
Please remove this comment. I noticed that variant/volteer/gpio. […]
Done
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 9: gpio_table
Please name this "override_gpio_table" to make it more clear that this is an override table and not […]
Done
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 193: gpio_table
Please change to "override_gpio_table".
Done
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 194: gpio_table
Please change to "override_gpio_table".
Done
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/42302/12/src/mainboard/google/volte... PS12, Line 17: device pci 15.0 on : chip drivers/i2c/generic : register "hid" = ""10EC5682"" : register "name" = ""RT58"" : register "desc" = ""Headset Codec"" : register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" : # Set the jd_src to RT5668_JD1 for jack detection : register "property_count" = "1" : register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" : register "property_list[0].name" = ""realtek,jd-src"" : register "property_list[0].integer" = "1" : device i2c 1a on : end : end : chip drivers/i2c/max98373 : register "vmon_slot_no" = "0" : register "imon_slot_no" = "1" : register "uid" = "0" : register "desc" = ""Right Speaker Amp"" : register "name" = ""MAXR"" : device i2c 31 on : end : end : chip drivers/i2c/max98373 : register "vmon_slot_no" = "2" : register "imon_slot_no" = "3" : register "uid" = "1" : register "desc" = ""Left Speaker Amp"" : register "name" = ""MAXL"" : device i2c 32 on : end : end : end # I2C #0 0xA0E8 :
Please rebase your change (https://review.coreboot. […]
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42302/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/terrador/gpio.c:
https://review.coreboot.org/c/coreboot/+/42302/13/src/mainboard/google/volte... PS13, Line 157: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ 'PRES' may be misspelled - perhaps 'PRESS'?
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 13: Code-Review+1
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 13:
Hi All, Could you help to review? Thanks.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
Patch Set 13: Code-Review+2
Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42302 )
Change subject: mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb ......................................................................
mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador.
BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Nick Vaccaro nvaccaro@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 256 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved David Wu: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index a54aeca..e49e2dc 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -1,23 +1,225 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <baseboard/gpio.h> +#include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h>
/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), };
-const struct pad_config *variant_base_gpio_table(size_t *num) +const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; }
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), };
const struct pad_config *variant_early_gpio_table(size_t *num) @@ -25,12 +227,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h index 0075826..fe512d8 100644 --- a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h @@ -5,6 +5,8 @@
#include <baseboard/gpio.h>
-/* Copied from baseboard and may need to change for the new variant. */ +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17
#endif diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 81da6bd..871ec24 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -4,7 +4,53 @@ # Enable Command Mirroring for controller 0 channel 0 and 1, # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + end + end + end # I2C #0 0xA0E8 device pci 15.1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000""
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