New patch to review for coreboot: 50f6be1 southbridge/amd/agesa/hudson: Add initial support for SMM

[Alexandru Gagniuc]

Alexandru Gagniuc ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5494

-gerrit

commit 50f6be198c93786917ccd956c2c9ee31e782e38b
Author: Alexandru Gagniuc 
Date:   Thu Apr 10 14:35:59 2014 -0500

southbridge/amd/agesa/hudson: Add initial support for SMM

This sets up the infrastructure to handle SMIs generated by the Hudson
    sothbridge. An API for interfacing to mainboard handlers is not
    defined at this point.

SMIs are always acknowledged and cleared, as not clearing an SMI will
    cause us to re-enter the SMI, effectively bricking the machine if a
    southbridge-generated SMI without a handler occurs.

Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619
    Signed-off-by: Alexandru Gagniuc 
---
 src/southbridge/amd/agesa/hudson/Makefile.inc |   2 +
 src/southbridge/amd/agesa/hudson/smihandler.c | 154 ++++++++++++++++++++++++++
 src/southbridge/amd/agesa/hudson/smm.c        |   9 ++
 3 files changed, 165 insertions(+)

diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 54a93d2..3211259 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -22,6 +22,8 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
 romstage-y += imc.c
 ramstage-y += imc.c

+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+ramstage-y += smm.c
 # ROMSIG At ROMBASE + 0x20000:
 # +-----------+---------------+----------------+------------+
 # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM    |
diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c
new file mode 100644
index 0000000..0c3001e
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/smihandler.c
@@ -0,0 +1,154 @@
+
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <arch/io.h>
+
+/* ACPI base is hardcoded by AGESA, and SMI BASE is at offset 0x200 from it */
+#define SMI_BASE 0xfed80200
+
+enum smi_source {
+	SMI_SOURCE_SCI = (1 << 0),
+	SMI_SOURCE_GPE = (1 << 1),
+	SMI_SOURCE_0x84 = (1 << 2),
+	SMI_SOURCE_0x88 = (1 << 3),
+	SMI_SOURCE_IRQ_TRAP = (1 << 4),
+	SMI_SOURCE_0x90 = (1 << 5)
+};
+
+static inline uint32_t smi_read32(uint8_t offset)
+{
+	return read32(SMI_BASE + offset);
+}
+
+static inline void smi_write32(uint8_t offset, uint32_t value)
+{
+	write32(SMI_BASE + offset, value);
+}
+
+static inline uint16_t smi_read16(uint8_t offset)
+{
+	return read16(SMI_BASE + offset);
+}
+
+static inline void smi_write16(uint8_t offset, uint16_t value)
+{
+	write16(SMI_BASE + offset, value);
+}
+
+void udelay(unsigned usecs)
+{
+	print_debug("udelay STUB!!!\n");
+	/* Stub */
+}
+
+int southbridge_io_trap_handler(int smif)
+{
+	return 0;
+}
+
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+{
+	print_debug("southbridge_smi_handler STUB!!!\n");
+	/* Stub */
+	u8 cunt = read8(0xfed80240);
+	if (++cunt == 23)
+		cunt++;
+	write8(0xfed80240, cunt);
+}
+
+static void process_smi_sci(void)
+{
+	uint32_t status;
+
+	status = smi_read32(0x10);
+
+	(void) status;
+
+	/* Clear events to prevent re-entering SMI if event isn't handled */
+	smi_write32(0x10, 0xffffffff);
+}
+
+static void process_gpe_smi(void)
+{
+	uint32_t status;
+
+	status = smi_read32(0x80);
+
+	(void) status;
+
+	/* Clear events to prevent re-entering SMI if event isn't handled */
+	smi_write32(0x80, 0xffffffff);
+}
+
+static void process_smi_0x84(void)
+{
+	uint32_t status;
+
+	status = smi_read32(0x84);
+
+	(void) status;
+
+	/* Clear events to prevent re-entering SMI if event isn't handled */
+	smi_write32(0x84, 0xffffffff);
+}
+
+static void process_smi_0x88(void)
+{
+	uint32_t status;
+
+	status = smi_read32(0x88);
+
+	(void) status;
+
+	/* Clear events to prevent re-entering SMI if event isn't handled */
+	smi_write32(0x88, 0xffffffff);
+}
+
+static void process_smi_0x8c(void)
+{
+	uint32_t status;
+
+	status = smi_read32(0x8c);
+
+	(void) status;
+
+	/* Clear events to prevent re-entering SMI if event isn't handled */
+	smi_write32(0x8c, 0xffffffff);
+}
+
+static void process_smi_0x90(void)
+{
+	uint32_t status;
+
+	status = smi_read32(0x90);
+
+	(void) status;
+
+	/* Clear events to prevent re-entering SMI if event isn't handled */
+	smi_write32(0x90, 0xffffffff);
+}
+
+void southbridge_smi_set_eos(void)
+{
+	uint16_t smi_src;
+
+	u32 reg = smi_read32(0x98);
+	reg |= (1 << 28);
+	smi_write32(0x98, reg);
+
+	smi_src = smi_read16(0x94);
+
+	if (smi_src & SMI_SOURCE_SCI)
+		process_smi_sci();
+	if (smi_src & SMI_SOURCE_GPE)
+		process_gpe_smi();
+	if (smi_src & SMI_SOURCE_0x84)
+		process_smi_0x84();
+	if (smi_src & SMI_SOURCE_0x88)
+		process_smi_0x88();
+	if (smi_src & SMI_SOURCE_IRQ_TRAP)
+		process_smi_0x8c();
+	if (smi_src & SMI_SOURCE_0x90)
+		process_smi_0x90();
+}
diff --git a/src/southbridge/amd/agesa/hudson/smm.c b/src/southbridge/amd/agesa/hudson/smm.c
new file mode 100644
index 0000000..a3a02ea
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/smm.c
@@ -0,0 +1,9 @@
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+	print_debug("smm_setup_structures STUB!!!\n");
+	/* Stub */
+}