New patch to review for coreboot: 30ce0db AMD/SB800: Define the GPP PCIe lane distribution

[Dave Frodin]

Dave Frodin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3104

-gerrit

commit 30ce0db66c861bdfc85ab9af8c7c21280764fe48
Author: Dave Frodin 
Date:   Wed Apr 17 18:21:09 2013 -0600

AMD/SB800: Define the GPP PCIe lane distribution

Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
    distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
    This fix was verified by openvoid on a AsRock E350M1 motherboard.

Change-Id: I0116c5f518e0d000be609013446e53da4112f586
    Signed-off-by: Dave Frodin 
---
 src/southbridge/amd/cimx/sb800/late.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index cfdf9f2..74b2d08 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -368,13 +368,13 @@ static void sb800_enable(device_t dev)
    	/* the first sb800 device */
    	switch (GPP_CFGMODE) { /* config the GPP PCIe ports */
    	case GPP_CFGMODE_X2200:
-			abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */
+			abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */
    		break;
    	case GPP_CFGMODE_X2110:
-			abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */
+			abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */
    		break;
    	case GPP_CFGMODE_X1111:
-			abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */
+			abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */
    		break;
    	case GPP_CFGMODE_X4000:
    	default: