[S] Change in coreboot[main]: device/pci_ids: Add Amstonlake CPU IDs.

[Harrie Paijmans (Code Review)]

Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87243?usp=email )

Change subject: device/pci_ids: Add Amstonlake CPU IDs.
......................................................................

device/pci_ids: Add Amstonlake CPU IDs.

Intel processor number X7433RE.
Based on docs 721616 rev 2.3.

BUG=NA
TEST=Boots on Intel Alderlake CRB with X7433RE processor

Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans 
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/include/soc/cpu.h
M src/soc/intel/common/block/systemagent/systemagent.c
6 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/87243/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 7d695b2..73a0c6c 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4427,6 +4427,9 @@
 #define PCI_DID_INTEL_ADL_N_ID_7		0x4679
 #define PCI_DID_INTEL_ADL_N_ID_8		0x467C
 #define PCI_DID_INTEL_ADL_N_ID_9		0x4677
+#define PCI_DID_INTEL_ASL_ID_1			0x4675
+#define PCI_DID_INTEL_ASL_ID_2			0x4674
+#define PCI_DID_INTEL_ASL_ID_3			0x4632
 #define PCI_DID_INTEL_MTL_M_ID			0x7D00
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 0c84d73..9b684d1 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -81,6 +81,9 @@
    { PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" },
    { PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" },
    { PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" },
+	{ PCI_DID_INTEL_ASL_ID_1, "Amstonlake" },
+	{ PCI_DID_INTEL_ASL_ID_2, "Amstonlake" },
+	{ PCI_DID_INTEL_ASL_ID_3, "Amstonlake" },
    { PCI_DID_INTEL_RPL_HX_ID_1, "Raptorlake-HX (8+16)" },
    { PCI_DID_INTEL_RPL_HX_ID_2, "Raptorlake-HX (8+12)" },
    { PCI_DID_INTEL_RPL_HX_ID_3, "Raptorlake-HX (8+8)" },
@@ -110,6 +113,7 @@
 } pch_table[] = {
    { PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
    { PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
+	{ PCI_DID_INTEL_ADP_M_N_ESPI_10, "Amstonlake SKU" },
    { PCI_DID_INTEL_ADP_S_ESPI_H610E, "AlderLake-S H610E" },
    { PCI_DID_INTEL_ADP_S_ESPI_Q670E, "AlderLake-S Q670E" },
    { PCI_DID_INTEL_ADP_S_ESPI_R680E, "AlderLake-S R680E" },
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 9e4ed52..c2efff3 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -249,6 +249,12 @@
    	PCI_DID_INTEL_ADL_N_ID_9,
    };

+	const uint16_t asl_mch_ids[] = {
+		PCI_DID_INTEL_ASL_ID_1,
+		PCI_DID_INTEL_ASL_ID_2,
+		PCI_DID_INTEL_ASL_ID_3,
+	};
+
    const uint16_t rpl_hx_mch_ids[] = {
    	PCI_DID_INTEL_RPL_HX_ID_1,
    	PCI_DID_INTEL_RPL_HX_ID_2,
@@ -298,6 +304,11 @@
    		return ADL_S;
    }

+	for (size_t i = 0; i < ARRAY_SIZE(asl_mch_ids); i++) {
+		if (asl_mch_ids[i] == mchid)
+			return ASL;
+	}
+
    for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) {
    	if (rpl_s_mch_ids[i] == mchid)
    		return RPL_S;
@@ -332,6 +343,7 @@
    case ADL_M: /* fallthrough */
    case ADL_N:
    case ADL_P:
+	case ASL:
    case RPL_P:
    	return LPM_S0i2_0 | LPM_S0i3_0;
    case ADL_S:
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 28c9169..380f40b 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -518,6 +518,9 @@
    case PCI_DID_INTEL_ADL_S_ID_10:
    case PCI_DID_INTEL_ADL_S_ID_11:
    case PCI_DID_INTEL_ADL_S_ID_12:
+	case PCI_DID_INTEL_ASL_ID_1:
+	case PCI_DID_INTEL_ASL_ID_2:
+	case PCI_DID_INTEL_ASL_ID_3:
    case PCI_DID_INTEL_RPL_HX_ID_1:
    case PCI_DID_INTEL_RPL_HX_ID_2:
    case PCI_DID_INTEL_RPL_HX_ID_3:
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index d081e85..36f966a 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -25,6 +25,7 @@
    ADL_N,
    ADL_P,
    ADL_S,
+	ASL,
    RPL_HX,
    RPL_P,
    RPL_S,
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 098c3c4..3a62735 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -538,6 +538,9 @@
    PCI_DID_INTEL_ADL_N_ID_7,
    PCI_DID_INTEL_ADL_N_ID_8,
    PCI_DID_INTEL_ADL_N_ID_9,
+	PCI_DID_INTEL_ASL_ID_1,
+	PCI_DID_INTEL_ASL_ID_2,
+	PCI_DID_INTEL_ASL_ID_3,
    PCI_DID_INTEL_RPL_HX_ID_1,
    PCI_DID_INTEL_RPL_HX_ID_2,
    PCI_DID_INTEL_RPL_HX_ID_3,