Attention is currently required from: Raul Rangel, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Christian Walter, Tim Wawrzynczak, Felix Held, Tim Chu. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58387 )
Change subject: [WIP] cpu/x86/lapic: Move LAPIC configuration to MP init ......................................................................
[WIP] cpu/x86/lapic: Move LAPIC configuration to MP init
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/model_6xx/model_6xx_init.c M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/model_f4x_init.c M src/cpu/qemu-x86/qemu.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/cpu.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c 39 files changed, 12 insertions(+), 117 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/58387/1
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 9539c3d..6329ad4 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -7,7 +7,6 @@ #include <cpu/amd/mtrr.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -59,9 +58,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 9d4da76..ee98b20 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -8,7 +8,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -58,9 +57,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 9fadc7e..939275b 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -7,7 +7,6 @@ #include <cpu/amd/mtrr.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -56,9 +55,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a5a8064..b82f514 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <device/pci.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <smp/node.h> @@ -41,9 +40,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - if (CONFIG(LOGICAL_CPUS)) { siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 6203922..0f482e4 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -4,7 +4,6 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include "common.h"
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 90db95b..ac771ea 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mp.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> @@ -540,9 +539,7 @@ /* Clear out pending MCEs */ configure_mca();
- /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic();
/* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 33187d7..02e6032 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -256,9 +255,6 @@ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(quad);
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 278d8de..4cf16d8 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -67,9 +66,6 @@ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states();
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f70d7b2..faa9231 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -7,7 +7,6 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> @@ -90,9 +89,7 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic();
/* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 09cad24..afd77d9 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -7,7 +7,6 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> @@ -337,9 +336,7 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic();
/* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index cf1394a..67157a8 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> @@ -19,9 +18,6 @@ x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 427d658..9760f5a 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> @@ -22,9 +21,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 3402c60..aa20f2d 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -26,9 +25,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index 2e7069c..842cb51 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -26,9 +25,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 16c6866..59651be 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -106,9 +105,6 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index d0987b4..038064a 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -120,9 +119,6 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states();
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 2e93507b..3c55ed5 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h>
@@ -16,9 +15,6 @@
/* Update the microcode */ intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index fc919a7..250acd4 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/common/common.h> @@ -23,9 +22,6 @@ intel_update_microcode_from_cbfs(); }
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index bf08d7b..b1a0dc0 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/common/common.h> @@ -23,9 +22,6 @@ intel_update_microcode_from_cbfs(); }
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ if (!CONFIG(PARALLEL_MP)) intel_sibling_init(cpu); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 5ebddc0..80bcf62 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -2,16 +2,12 @@
#include <device/device.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h>
static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 9f01007..f0cdb58 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -2,11 +2,9 @@
#include <cpu/cpu.h> #include <device/device.h> -#include <cpu/x86/lapic.h>
static void qemu_cpu_init(struct device *dev) { - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 9003534..b73679f 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -71,7 +71,7 @@ return CONFIG(SMP) || CONFIG(IOAPIC); }
-static void lapic_virtual_wire_mode_init(void) +void setup_lapic_interrupts(void) { /* * Set Task Priority to 'accept all'. diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index bc0f44f..f2587fd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -299,6 +299,11 @@ cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); #endif + + /* Ensure the local APIC is enabled */ + enable_lapic(); + setup_lapic_interrupts(); + cpu_initialize(index);
spin_unlock(&start_cpu_lock); @@ -408,8 +413,10 @@ info = cpu_info();
/* Ensure the local APIC is enabled */ - if (is_smp_boot()) + if (is_smp_boot()) { enable_lapic(); + setup_lapic_interrupts(); + }
/* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 8fb7d39..ea4bd94 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -187,6 +187,7 @@
/* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts();
info = cpu_info(); info->index = cpu; @@ -570,6 +571,7 @@
/* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts();
/* Set the device path of the boot CPU. */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 537fa97..0701dbc 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -158,6 +158,6 @@
void enable_lapic(void); void disable_lapic(void); -void setup_lapic(void); +void setup_lapic_interrupts(void);
#endif /* CPU_X86_LAPIC_H */ diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 2ac30b6..000d9a0 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -61,7 +60,6 @@ static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr();
amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index b04d004..68ac4d5 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,7 +10,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -65,7 +64,6 @@ static void model_17_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr();
amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9283ff7..6a117d8 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -9,7 +9,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -65,7 +64,6 @@ static void model_15_init(struct device *dev) { check_mca(); - setup_lapic();
/* * Per AMD, sync an undocumented MSR with the PSP base address. diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 801d10d..a654400 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -69,9 +68,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f2b14d7..6d85ab2 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -5,7 +5,6 @@ #include <console/console.h> #include "chip.h" #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> @@ -145,8 +144,6 @@ x86_setup_mtrrs_with_detect(); x86_mtrr_check();
- /* Enable the local CPU apics */ - setup_lapic(); }
#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 0c6f463..748cd18 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -7,7 +7,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -34,9 +33,6 @@ { printk(BIOS_DEBUG, "Init Braswell core.\n");
- /* Enable the local cpu apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 8c8cad0..5af0d9b 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -109,9 +108,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure c-state interrupt response time */ configure_c_states(cfg); diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 0788c67..8b155d1 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -4,7 +4,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> #include <cpu/intel/common/common.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <device/pci.h> @@ -62,9 +61,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 3ca2172..5bcb51a 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -95,9 +94,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index a58fe55..232ee89 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -62,9 +61,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3abf19b..9a82aec 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> @@ -107,9 +106,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 084b5d6..aaff270 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -8,7 +8,6 @@
#include <console/console.h> #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -68,9 +67,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 19bf2af..9bb08cc 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -3,7 +3,6 @@ #include <arch/ioapic.h> #include <console/console.h> #include <console/debug.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -181,7 +180,6 @@ override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); - setup_lapic(); p2sb_unhide(); }
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cfd9e5c..d8d43f8 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -11,7 +11,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <intelblocks/cpulib.h> @@ -71,7 +70,6 @@
printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); - setup_lapic();
/* * Set HWP base feature, EPP reg enumeration, lock thermal and msr
-
Kyösti Mälkki (Code Review)