Change in ...coreboot[master]: sb/intel/fsp_rangeley: Fix typo in GPIO Level

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30675

Change subject: sb/intel/fsp_rangeley: Fix typo in GPIO Level
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sb/intel/fsp_rangeley: Fix typo in GPIO Level

Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/fsp_rangeley/acpi/soc.asl
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30675/1

diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
index b55bd92..dde6796 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@@ -93,7 +93,7 @@
    	GIO2, 8,
    	GIO3, 8,
    	Offset(0x0c),	// GPIO Level
-		GL00, 1,
+		GP00, 1,
    	GP01, 1,
    	GP02, 1,
    	GP0e, 1,