Change in coreboot[master]: soc/intel/alderlake: Update CPU and IGD Device IDs

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54211 )

Change subject: soc/intel/alderlake: Update CPU and IGD Device IDs
......................................................................

soc/intel/alderlake: Update CPU and IGD Device IDs

Updated CPU ID and IGD ID for Alder Lake as per EDS.

TEST=Code compilation works and coreboot is able to boot and identify
new device Ids.

Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Tim Wawrzynczak 
---
M src/include/device/pci_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
5 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a3ee558..1a9aa35 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3812,6 +3812,7 @@
 #define PCI_DEVICE_ID_INTEL_ADL_GT1_8			0x4618
 #define PCI_DEVICE_ID_INTEL_ADL_GT1_9			0x4619
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2			0x46a0
+#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1			0x46b0
 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1			0x4680
 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1			0x46c0

diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 2666426..78f02ec 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -23,6 +23,7 @@
    const char *name;
 } cpu_table[] = {
    { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" },
+	{ CPUID_ALDERLAKE_P_B0, "Alderlake-P B0" },
    { CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" },
 };

@@ -98,6 +99,7 @@
    { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" },
    { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" },
    { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" },
    { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
 };

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 9619298..7e8c199 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -68,6 +68,7 @@
    { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_B0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_M_A0 },
    { 0, 0 },
 };
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 0920a05..fe89f86 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -295,6 +295,7 @@
    PCI_DEVICE_ID_INTEL_ADL_GT1_8,
    PCI_DEVICE_ID_INTEL_ADL_GT1_9,
    PCI_DEVICE_ID_INTEL_ADL_P_GT2,
+	PCI_DEVICE_ID_INTEL_ADL_P_GT2_1,
    PCI_DEVICE_ID_INTEL_ADL_S_GT1,
    PCI_DEVICE_ID_INTEL_ADL_M_GT1,
    0,
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index 9038dd5..3d8290f 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -46,6 +46,7 @@
 #define CPUID_ELKHARTLAKE_B0	0x90661
 #define CPUID_ALDERLAKE_S_A0	0x90670
 #define CPUID_ALDERLAKE_P_A0	0x906a0
+#define CPUID_ALDERLAKE_P_B0	0x906a2
 #define CPUID_ALDERLAKE_M_A0	0x906a1
 /*
  * MP Init callback function to Find CPU Topology. This function is common